JAJSNN8A January   2024  – August 2024 THVD2419 , THVD2429

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings - IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics 250kbps
    9. 6.9  Switching Characteristics 20Mbps
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Electrostatic Discharge (ESD) Protection
      2. 8.3.2 Electrical Fast Transient (EFT) Protection
      3. 8.3.3 Surge Protection
      4. 8.3.4 Enhanced Receiver Noise Immunity
      5. 8.3.5 Failsafe Receiver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Switching Characteristics 20Mbps

20Mbps (THVD2429) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V, VIO = 3.3 V, unless otherwise noted. (1) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
tr, tf Differential output rise/fall time RL = 54Ω, CL = 50pF
See Figure 7-3		 3.5 5 15 ns
tPHL, tPLH Propagation delay RL = 54Ω, CL = 50pF
See Figure 7-3		 6 15 30 ns
tSK(P) Pulse skew, |tPHL – tPLH| RL = 54Ω, CL = 50pF
See Figure 7-3		 0.5 3 ns
tPHZ, tPLZ Disable time See Figure 7-4 and Figure 7-5 RE = X 20 35 ns
tPZH, tPZL Enable time RE = 0V 16 40 ns
RE = VIO 2.5 4.5 μs
tSHDN Time to shutdown RE = VIO 50 500 ns
Receiver
tr, tf Output rise/fall time CL = 15pF, See Figure 7-6 1.5 6 ns
tPHL, tPLH Propagation delay 25 35 60 ns
tSK(P) Pulse skew, |tPHL – tPLH| 5.5 ns
tPHZ, tPLZ Disable time DE = X 18 25 ns
tPZH(1),
tPZL(1)		 Enable time See Figure 7-7 DE = VIO 55 82 ns
tPZH(2),
tPZL(2)		 Enable time See Figure 7-8 DE = 0V 2.5 4.5 μs
tD(OFS) Delay to enter fail-safe operation See Figure 7-9 CL = 15pF 7 10 18 μs
tD(FSO) Delay to exit fail-safe operation 19 35 50 ns
tSHDN Time to shutdown See Figure 7-8 DE = 0V 50 500 ns
(1) A, B are driver output and receiver input terminals for Half duplex devices. A, B are RX input, Y/Z are driver output terminals for Full duplex device