JAJSOB4A November   2023  – March 2024 THVD2412 , THVD2442

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_250kbps
    9. 5.9  Switching Characteristics_20Mbps
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70-V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input D. A logic high at D causes Y to turn high and Z to turn low. In this case, the differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.

Table 7-1 Driver Function Table
INPUT ENABLE OUTPUTS FUNCTION
D DE Y Z
H H H L Actively drive bus high
L H L H Actively drive bus low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus high by default

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH-, the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go fail-safe high when the transceiver is disconnected from the bus (open-circuit), or the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Table 7-2 Receiver Function Table
DIFFERENTIAL INPUT ENABLE OUTPUT FUNCTION
VID = VA – VB RE R
VTH+ < VID L H Receive valid bus high
VTH- < VID < VTH+ L ? Indeterminate bus state
VID < VTH- L L Receive valid bus low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output