JAJSQY1B August   2023  – April 2024 THVD4431

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_RS-485_500kbps
    9. 5.9  Switching Characteristics_RS-485_20Mbps
    10. 5.10 Switching Characteristics, Driver_RS232
    11. 5.11 Switching Characteristics, Receiver_RS232
    12. 5.12 Switching Characteristics_MODE switching
    13. 5.13 Switching Characteristics_RS-485_Termination resistor
    14. 5.14 Switching Characteristics_Loopback mode
    15. 5.15 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Integrated IEC ESD and EFT Protection
      2. 7.3.2 Protection Features
      3. 7.3.3 RS-485 Receiver Fail-Safe Operation
      4. 7.3.4 Low-Power Shutdown Mode
      5. 7.3.5 On-chip Switchable Termination Resistor
      6. 7.3.6 Operational Data Rate
      7. 7.3.7 Diagnostic Loopback
      8. 7.3.8 Integrated Charge pump for RS-232
    4. 7.4 Device Functional Modes
      1. 7.4.1 RS-485 Functionality
      2. 7.4.2 RS-232 Functionality
      3. 7.4.3 Mode Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length for RS-485
        2. 8.2.1.2 Stub Length for RS-485 Network
        3. 8.2.1.3 Bus Loading for RS-485 Network
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.14 Switching Characteristics_Loopback mode

Parameters over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V , VIO = 3.3 V, unless otherwise noted. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLB_RS232_rising Delay from Logic input rising edge to logic output rising edge in RS-232 Loopback mode MODE2 = X, MODE1, MODE0 = GND; SLR = GND, Delay from 50% of L3/L4/L6 rising edge to 50% L2/L1/L5, L7, L8 rising edge, SHDN = Vio, TERM_TX and TERM_RX float, Load capacitance on output buffers = 15 pF, RL on all 3 driver outputs = 3kΩ, -40 ℃ ≤ TA ≤ 85 ℃ 410 920 ns
MODE2 = X, MODE1, MODE0 = GND; SLR = Vio, Delay from 50% of L3/L4/L6 rising edge to 50% L2/L1/L5, L7, L8 rising edge, SHDN = Vio, TERM_TX and TERM_RX float, Load capacitance on output buffers = 15 pF, RL on all 3 driver outputs = 3kΩ, -40 ℃ ≤ TA ≤ 85 ℃ 640 1100 ns
tLB_RS232_falling Delay from Logic input falling edge to logic output falling edge in RS-232 Loopback mode MODE2 = X, MODE1, MODE0 = GND; SLR = GND, Delay from 50% of L3/L4/L6 falling edge to 50% L2/L1/L5, L7, L8 falling edge, SHDN = Vio, TERM_TX and TERM_RX float, Load capacitance on output buffers = 15 pF, RL on all 3 driver outputs = 3kΩ, -40 ℃ ≤ TA ≤ 85 ℃ 570 760 ns
MODE2 = X, MODE1, MODE0 = GND; SLR = Vio, Delay from 50% of L3/L4/L6 falling edge to 50% L2/L1/L5, L7, L8 falling edge, SHDN = Vio, TERM_TX and TERM_RX float, Load capacitance on output buffers = 15 pF, RL on all 3 driver outputs = 3kΩ, -40 ℃ ≤ TA ≤ 85 ℃ 600 1460 ns
tSKEW_RS232_LB Pulse skew from logic input to logic output in RS232 loopback mode |tLB_RS232_rising - tLB_RS232_falling|, SLR = Vio, -40 ℃ ≤ TA ≤ 85 ℃ 100 860 ns
|tLB_RS232_rising - tLB_RS232_falling|, SLR = GND, -40 ℃ ≤ TA ≤ 85 ℃ 70 250 ns
tLB_RS485_rising Delay from Logic input rising edge to logic output rising edge in RS-485 Loopback mode MODE2 = MODE1 = MODE0 = Vio; SLR = Vio, Delay from 50% of L3 rising edge to 50% L2 rising edge, SHDN = Vio, TERM_TX and TERM_RX float, Load cap on L2 = 15 pF, Load on Driver output terminals (R2-R1) = 54 Ω  1060 1770 ns
tLB_RS485_falling Delay from Logic input falling edge to logic output falling edge in RS-485 Loopback mode MODE2 = MODE1 = MODE0 = Vio; SLR = Vio, Delay from 50% of L3 falling edge to 50% L2 falling edge, SHDN = Vio, TERM_TX and TERM_RX float, Load cap on L2 = 15 pF, Load on Driver output terminals (R2-R1) = 54 Ω 1060 1770 ns
tSKEW_RS485_LB   Pulse skew from logic input to logic output in RS485 loopback mode |tLB_RS485_rising - tLB_RS485_falling|, SLR = Vio  5 50 ns