JAJSDS2A September 2017 – February 2022 TIC10024-Q1
PRODUCTION DATA
During normal operation of a typical 12 V automotive system, the VS voltage is usually quite stable and stays well above 11 V. However, the VS voltage may drop temporarily during certain vehicle operations, such as cold cranking. If the VS voltage drops below VUV_F, the TIC10024-Q1 enters the under-voltage (UV) condition since there is not enough voltage headroom for the device to accurately generate wetting currents. The following describes the behavior of the TIC10024-Q1 under UV condition:
Note the device resets as described in section VS Supply POR if the VS voltage drops below VPOR_F.
When the VS voltage rises above VUV_R, the INT pin is asserted low to notify the microcontroller that the UV condition no longer exists. The UV bit in the register INT_STAT is flagged to logic 1 and the bit UV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the UV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT pin is released afterwards.
The following diagram describes the TIC10024-Q1 operation at various different VS voltages. If the VS voltage stays above VUV_F (Case 1), the device stays in normal operation. If the VS voltage drops below VUV_F but stays above VPOR_F (Case 2), the device enters the UV condition. If VS voltage drops below VPOR_F (Case 3), the device resets and all register settings are cleared. The microcontroller is then required to re-program all the configuration registers in order to resume normal operation after the VS voltage recovers.