JAJSDS2 データシート

JAJSDS2A September 2017 – February 2022 TIC10024-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DCP|38
- MPDS520B

サーマルパッド・メカニカル・データ

DCP|38
- PPTD170A

発注情報

6.5 Electrical Characteristics

over operating free-air temperature range, V_S = 4.5 V to 35 V, and V_DD = 3 V to 5.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
I_{S_CONT}	Continuous mode V_S power supply current	Continuous mode, I_WETT= 10 mA, all switches open, no active comparator operation, no unserviced interrupt			5.6	7	mA
I_{S_POLL_COMP_25}	Polling mode V_S power supply average current	T_A= 25°	Polling mode, t_POLL= 64 ms, t_POLL_ACT= 128 µs, all switches open, I_WETT= 10 mA, no unserviced interrupt		68	100	µA
I_{S_POLL_COMP_85}		T_A= -40° to 85°C			68	110	µA
I_{S_POLL_COMP}		T_A= -40° to 125°C			68	170	µA
I_{S_RESET}	Reset mode V_S power supply current	Reset mode, V_RESET= V_DD. V_S= 12 V, all switches open, T_A=25°C			12	17	µA
I_{S_IDLE_25}	V_S power supply average current in idle state	TRIGGER bit in CONFIG register = logic 0, T_A= 25°C, no unserviced interrupt			50	75	µA
I_{S_IDLE_85}		TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 85°C, no unserviced interrupt			50	95	µA
I_{S_IDLE}		TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 125°C, no unserviced interrupt			50	145	µA
I_DD	Logic supply current from V_DD	SCLK = SI = 0 V, CS = INT = V_DD, no SPI communication			1.5	10	µA
V_{POR_R}	Power on reset (POR) voltage for V_S	Threshold for rising V_S from device OFF condition resulting in INT pin assertion and a flagged POR bit in the INT_STAT register		3.85		4.5	V
V_{POR_F}	Power on reset (POR) voltage for V_S	Threshold for falling V_S from device normal operation to reset mode and loss of SPI communication		1.95		2.8	V
V_{OV_R}	Over-voltage (OV) condition for V_S	Threshold for rising V_S from device normal operation resulting in INT pin assertion and a flagged OV bit in the INT_STAT register		35		40	V
V_{OV_HYST}	Over-voltage (OV) condition hysteresis for V_S			1		3.5	V
V_{UV_R}	Under-voltage (UV) condition for V_S	Threshold for rising V_S from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register		3.85		4.5	V
V_{UV_F}	Under-voltage (UV) condition for V_S	Threshold for falling V_S from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register		3.7		4.4	V
V_{UV_HYST}	Under-voltage (UV) condition hysteresis for V_S⁽¹⁾			75		275	mV
V_{DD_F}		Threshold for falling V_DD resulting in loss of SPI communication		2.5		2.9	V
V_{DD_HYST}	Valid V_DD voltage hysteresis			50		150	mV
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤ 100Ω , MINIMUM RESISTANCE VALUE WITH SWITCH OPEN ≥ 5000 Ω)
I_WETT (CSO)	Wetting current accuracy for CSO (switch closed)	1 mA setting	4.5 V ≤ V_S ≤ 35 V	0.84	1	1.14	mA
		2 mA setting	4.5 V ≤ V_S ≤ 35 V	1.71	2	2.32
		5 mA setting	4.5 V ≤ V_S < 5 V	2.39		5.5
		5 mA setting	5 V ≤ V_S ≤ 35 V	4.3	5	5.6
		10 mA setting	4.5 V ≤ V_S < 6 V	2.4		11
		10 mA setting	6 V ≤ V_S ≤ 35 V	8.4	10	11.4
		15 mA setting	4.5 V ≤ V_S < 6.5 V	2.4		16.5
		15 mA setting	6.5 V ≤ V_S ≤ 35 V	12.5	15	17
I_WETT (CSI)	Wetting current accuracy for CSI (switch closed)	1 mA setting	4.5 V ≤ V_S ≤ 35 V	0.75	1.1	2.05	mA
		2 mA setting		1.6	2.2	3.3
		5 mA setting		4.3	5.6	7.1
		10 mA setting		9.2	11.5	13.4
		15 mA setting	4.5 V ≤ V_S < 6 V	11	16.5	19.2
		15 mA setting	6 V ≤ V_S ≤ 35V	13.7	16.5	19.2
V_{CSI_DROP_OPEN}	Voltage drop from IN_x pin to AGND across CSI (switch open)	10 mA setting, R_SW= 5kΩ	4.5 V ≤ V_S ≤ 35V			1.7	V
V_{CSI_DROP_OPEN}	Voltage drop from IN_x pin to AGND across CSI (switch open)	15 mA setting, R_SW= 5kΩ	4.5 V ≤ V_S ≤ 35V			1.7	V
V_{CSI_DROP_CLOSED}	Voltage drop from INx pin to ground across CSI (switch closed)	2mA setting, I_IN= 1mA (4.5V ≤ VS ≤ 35V)	4.5 V ≤ V_S ≤ 35V			1.2	V
		5mA setting, I_IN= 1mA or 2mA				1.3	V
		10mA setting, I_IN= 1mA, 2mA, or 5mA				1.5	V
		15mA setting, I_IN= 1mA, 2mA, 5mA, or 10mA				2.1	V
LEAKAGE CURRENTS
I_{IN_LEAK_OFF}	Leakage current at input INx when channel is disabled	0 V ≤ V_INx ≤ V_S , channel disabled (EN_INx register bit= logic 0)		-4		5.3	µA
I_{IN_LEAK_OFF_25}	Leakage current at input INx when channel is disabled	0 V ≤ V_INx ≤ V_S , channel disabled (EN_INx register bit= logic 0), T_A = 25°C		-0.5		0.5	µA
I_{IN_LEAK_0mA}	Leakage current at input INx when wetting current setting is 0mA	0 V ≤ V_INx ≤ 6 V, 6 V ≤ V_S ≤ 35 V , I_WETT setting = 0 mA		-110		110	µA
I_{IN_LEAK_0mA}		0 V ≤ V_INx ≤ 6 V, 6 V ≤ V_S ≤ 35 V , I_WETT setting = 0 mA		-110		110	µA
I_{IN_LEAK_LOSS_OF_GND}	Leakage current at input INx under loss of GND condition	V_S = 24 V, 0 V ≤ V_INx ≤ 24 V, all grounds (AGND, DGND, and EP) = 24 V, V_DD shorted to the grounds⁽¹⁾		-5			µA
I_{IN_LEAK_LOSS_OF_VS}	Leakage current at input INx under loss of V_S condition	0 V ≤ V_INx ≤ 24 V, V_S shorted to the grounds = 0 V, V_DD = 0 V				5	µA
LOGIC LEVELS
V_{/INT_L}	INT output low voltage	I_/INT = 2 mA				0.35	V
V_{/INT_L}	INT output low voltage	I_/INT = 4 mA				0.6	V
V_{SO_L}	SO output low voltage	I_SO = 2 mA				0.2V_DD	V
V_{SO_H}	SO output high voltage	I_SO = -2 mA		0.8V_DD			V
V_{IN_L}	SI, SCLK, and CS input low voltage					0.3V_DD	V
V_{IN_H}	SI, SCLK, and CS input high voltage			0.7V_DD			V
V_{RESET_L}	RESET input low voltage					0.8	V
V_{RESET_H}	RESET input high voltage			1.6			V
R_{RESET_25}	RESET pin internal pull-down resistor	V_RESET= 0 to 5.5V, T_A = 25°C		0.85	1.25	1.7	MΩ
R_RESET	RESET pin internal pull-down resistor	V_RESET= 0 to 5.5V, T_A = –40° to 125°C		0.2		2.1	MΩ
COMPARATOR PARAMETERS
V_{TH_ COMP_2V}	Comparator threshold for 2 V	THRES_COMP = 2 V		1.85		2.25	V
V_{TH_ COMP_2p7V}	Comparator threshold for 2.7 V	THRES_COMP = 2.7 V		2.4		2.9	V
V_{TH_ COMP_3V}	Comparator threshold for 3 V	THRES_COMP = 3 V		2.85		3.3	V
V_{TH_ COMP_4V}	Comparator threshold for 4 V	THRES_COMP = 4 V		3.7		4.35	V
V_{S_COMP}	Minimum V_S requirement for proper detection	THRES_COMP = 2 V		4.5			V
		THRES_COMP = 2.7 V		5
		THRES_COMP = 3 V		5.5
		THRES_COMP = 4 V		6.5
R_{IN, COMP}	Comparator equivalent input resistance	THRES_COMP = 2 V		30	130		kΩ
		THRES_COMP = 2.7 V		35	130
		THRES_COMP = 3 V		35	105
		THRES_COMP = 4 V		43	95

(1) Specified by design.