JAJSDS2A September   2017  – February 2022 TIC10024-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Enable Selection
        3. 8.3.8.3 Thresholds Adjustment
        4. 8.3.8.4 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
  9. 9 Programming
    1. 9.1 SPI Communication Interface Buses
      1. 9.1.1 Chip Select ( CS)
      2. 9.1.2 System Clock (SCLK)
      3. 9.1.3 Slave In (SI)
      4. 9.1.4 Slave Out (SO)
    2. 9.2 SPI Sequence
      1. 9.2.1 Read Operation
      2. 9.2.2 Write Operation
      3. 9.2.3 Status Flag
    3. 9.3 Programming Guidelines
    4. 9.4 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Switch Detection in Automotive Body Control Module
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Using TIC10024-Q1 in a 12 V Automotive System
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.1 Using TIC10024-Q1 in a 12 V Automotive System

GUID-7FCC01E8-8B1F-4A86-9B2B-67DFD48593EA-low.gifFigure 10-3 Typical System Diagram of Battery Connections for TIC10024-Q1

The TIC10024-Q1 is designed to operate with a 12 V automotive system. Figure 10-3 depicts a typical system diagram to show how the device is connected to the battery. Please remember to be careful when connecting the battery directly to the device on the VS supply pin (through a reverse-blocking diode) or the input (INX) pins since an automotive battery can be subjected to various transient and over-voltage events. Manufacturers have independently created standards and test procedures in an effort to prevent sensitive electronics from failing due to these events. Recently, combined efforts are made with ISO to develop the ISO 16750-2 standard (Road vehicles -- Environmental conditions and testing for electrical and electronic equipment -- Part 2: Electrical loads), which describe the possible transients that could occur to an automotive battery and specify test methods to simulate them.

It shall be noted that the TIC10024-Q1 is designed and tested according to the ISO 16750-2 standard. A few voltage stress tests and their test conditions are listed below. Exposing the device to more severe transient events than described by the standard can potentially causes performance degradation and long-term damage to the device.

  • Direct current supply voltage: VBAT, min = 6 V; VBAT, max= 16 V
  • To emulate a jump start event, voltage profile described in Figure 10-4 is used.
GUID-07B1DBD4-9550-4372-88A6-E66B2D8EDF04-low.gif Figure 10-4 Voltage Profile to Test a Jump Start Event
Table 10-3 Voltage Profile Parameters to Test a Jump Start Event
Parameter Value
VBAT, min 10.8 V
VBAT, max 24 V
tr < 10 ms
t1 60 s ± 6 s
tf < 10 ms
Number of cycles 1

To emulate a load dump event for an alternator with centralized load dump suppression, voltage profile described in Figure 10-5 is used. UA and US* are applied directly to VBAT.

Figure 10-5 Voltage Profile to Test a Load Dump Event With Centralized Load Dump Suppression
Table 10-4 Voltage Profile to Test a Load Dump Event With Centralized Load Dump Suppression
Parameter Value
UA 13.5 V
US 79 V ≤ US ≤ 101
US* 35 V
td 40 ms ≤ td ≤ 400 ms
tr < 10 ms
Number of cycles 5 pulses at intervals of 1 min

To emulate a cranking event, voltage profile describe in Figure 10-6 is used. US, US6, and UA are applied directly to VBAT.

Figure 10-6 Voltage Profile to Test a Cranking Event
Table 10-5 Voltage Profile Used to Test a Cranking Event
Parameter Value - Level I Value - Level II Value - Level IV
US6 8 V 4.5 V 6 V
US 9.5 V 6.5 V 6.5 V
UB 14 V ± 0.2 V 14 V ± 0.2 V 14 V ± 0.2 V
tf 5 ms ± 0.5 ms 5 ms ± 0.5 ms 5 ms ± 0.5 ms
t6 15 ms ± 1.5 ms 15 ms ± 1.5 ms 15 ms ± 1.5 ms
t7 50 ms ± 5 ms 50 ms ± 5 ms 50 ms ± 5 ms
t8 1000 ms ± 100 ms 10000 ms ± 1000 ms 10000 ms ± 1000 ms
tr 40 ms ± 4 ms 100 ms ± 10 ms 100 ms ± 10 ms