JAJSDS2A September   2017  – February 2022 TIC10024-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Enable Selection
        3. 8.3.8.3 Thresholds Adjustment
        4. 8.3.8.4 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
  9. 9 Programming
    1. 9.1 SPI Communication Interface Buses
      1. 9.1.1 Chip Select ( CS)
      2. 9.1.2 System Clock (SCLK)
      3. 9.1.3 Slave In (SI)
      4. 9.1.4 Slave Out (SO)
    2. 9.2 SPI Sequence
      1. 9.2.1 Read Operation
      2. 9.2.2 Write Operation
      3. 9.2.3 Status Flag
    3. 9.3 Programming Guidelines
    4. 9.4 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Switch Detection in Automotive Body Control Module
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Using TIC10024-Q1 in a 12 V Automotive System
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.9.1 INT Pin Assertion Scheme

TIC10024-Q1 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be adjusted by configuring the INT_CONFIG bit in the CONFIG register.

If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as illustrated in Figure 8-5.

Figure 8-5 Static INT Assertion Scheme

In some system implementations an edge-triggered based microcontroller might potentially miss the INT assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC10024-Q1 provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used (INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of tINT_ACTIVE and is de-asserted back to high if the INT_STAT register has not been read after tINT_ACTIVE has elapsed. The INT is kept high for a duration of tINT_INACTIVE, and is re-asserted low after tINT_INACTIVE has elapsed. The INT pin continues to toggle until the INT_STAT register is read.

If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s CS rising edge and the content of the INT_STAT register is also cleared, as shown in Figure 8-6. If the INT_STAT register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in Figure 8-7.

Figure 8-6 Dynamic INT Assertion Scheme With INT_STAT Register Read During tINT_ACTIVE
Figure 8-7 Dynamic INT Assertion Scheme With INT_STAT Register Read During tINT_INACTIVE

The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can only be changed when bit TRIGGER is logic 0 in the CONFIG register.