JAJSDS2A September   2017  – February 2022 TIC10024-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Enable Selection
        3. 8.3.8.3 Thresholds Adjustment
        4. 8.3.8.4 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
  9. 9 Programming
    1. 9.1 SPI Communication Interface Buses
      1. 9.1.1 Chip Select ( CS)
      2. 9.1.2 System Clock (SCLK)
      3. 9.1.3 Slave In (SI)
      4. 9.1.4 Slave Out (SO)
    2. 9.2 SPI Sequence
      1. 9.2.1 Read Operation
      2. 9.2.2 Write Operation
      3. 9.2.3 Status Flag
    3. 9.3 Programming Guidelines
    4. 9.4 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Switch Detection in Automotive Body Control Module
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Using TIC10024-Q1 in a 12 V Automotive System
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.12 Cyclic Redundancy Check (CRC)

The TIC10024-Q1 includes a CRC module to support redundancy checks on the configuration registers to ensure the integrity of data. The CRC calculation is based on the ITU-T X.25 implementation, and the CRC polynomial (0x1021) used is popularly known as CRC-CCITT-16 since it was initially proposed by the ITU-T (formerly CCITT) committee. The CRC calculation rule is defined in Table 8-3:

Table 8-3 CRC Calculation Rule
CRC RULEVALUE
CRC result width16 bits
Polynomialx16 + x12 + x5 +1 (1021h)
Initial (seed) valueFFFFh
Input data reflectedNo
Result data reflectedNo
XOR value0000h

The CRC calculation is done on all the configuration registers starting from register CONFIG and ending at register INT_EN_CFG0 (address 1Ah through 24h). The device substitutes a “zero” for each reserved configuration register bit during the CRC calculation. The CRC calculation can be triggered by asserting the CRC_T bit in the CONFIG register. Once completed, the CRC_CALC interrupt bit in the INT_STAT register is asserted and an interrupt is issued. The 16-bit CRC calculation result is stored in the register CRC. This interrupt can be disabled by de-asserting the CRC_CALC_EN bit in the INT_EN_CFG0 register. It is important to avoid writing data to the configuration registers when the device is undergoing CRC calculations to prevent false calculation results.

Figure 8-10 shows the block diagram of the CRC module. The module consists of 16 shift-registers and 3 exclusive-OR gates. The registers start with 1111-1111-1111-1111 (or FFFFh) and the module performs an XOR function and shifts its content until the last bit of the register string is used. The final register’s content after the last data bit is the calculated CRC value of the data set and the content is stored in the CRC register.

Note the CRC_T bit self-clears after the CRC calculation is completed. Logic 1 is used for CRC_T bit during CRC calculation.

GUID-D5AB9495-5EBD-43AD-83AE-2F6FD3DED04A-low.gifFigure 8-10 CCITT-16 CRC Module Block Diagram