JAJSDS2A September 2017 – February 2022 TIC10024-Q1
PRODUCTION DATA
If VS voltage rises above VOV_R, the TIC10024-Q1 enters the over-voltage (OV) condition to prevent damage to internal structures of the device on the VS and INx (for battery-connected switches) pins. The following describes the behavior of the TIC10024-Q1 under OV condition:
When the VS voltage drops below VOV_R - VOV_HYST, the INT pin is asserted low to notify the microcontroller that the over-voltage condition no longer exists. The OV bit in the register INT_STAT is flagged to logic 1 and the bit OV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the OV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared and the INT pin is released afterwards.