JAJSJD1D
February 2022 – March 2023
TIOL112
,
TIOL1123
,
TIOL1125
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
ESD Ratings - IEC Specifications
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
Wake-Up Detection
8.3.2
Current Limit Configuration
8.3.3
Current Fault Detection, Indication and Auto Recovery
8.3.4
Thermal Warning, Thermal Shutdown
8.3.5
Fault Reporting (NFAULT)
8.3.6
Transceiver Function Tables
8.3.7
The Integrated Voltage Regulator (LDO)
8.3.8
Reverse Polarity Protection
8.3.9
Integrated Surge Protection and Transient Waveform Tolerance
8.3.10
Power Up Sequence (TIOL112)
8.3.11
Undervoltage Lock-Out (UVLO)
8.4
Device Functional Modes
8.4.1
NPN Configuration (N-Switch SIO Mode)
8.4.2
PNP Configuration (P-Switch SIO Mode)
8.4.3
Push-Pull, Communication Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Maximum Junction Temperature Check
9.2.2.2
Driving Capacitive Loads
9.2.2.3
Driving Inductive Loads
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
サポート・リソース
10.3
Trademarks
10.4
静電気放電に関する注意事項
10.5
用語集
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DRC|10
MPDS117L
サーマルパッド・メカニカル・データ
DRC|10
QFND647
発注情報
jajsjd1d_oa
jajsjd1d_pm
9.4.2
Layout Example
Figure 9-9
Layout Example