JAJSKP0B february   2022  – june 2023 TIOS102 , TIOS1023 , TIOS1025

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Current Limit Configuration
      2. 8.3.2  Current Fault Detection, Indication and Auto Recovery
      3. 8.3.3  Thermal Warning, Thermal Shutdown
      4. 8.3.4  Fault Reporting (NFAULT)
      5. 8.3.5  Device Function Tables
      6. 8.3.6  The Integrated Voltage Regulator (LDO)
      7. 8.3.7  Reverse Polarity Protection
      8. 8.3.8  Integrated Surge Protection and Transient Waveform Tolerance
      9. 8.3.9  Power Up Sequence
      10. 8.3.10 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch Mode)
      2. 8.4.2 PNP Configuration (P-Switch Mode)
      3. 8.4.3 Push-Pull Mode
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 最大接合部温度チェック
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.8 Integrated Surge Protection and Transient Waveform Tolerance

The VCC and OUT pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply decoupling capacitor between VCC and GND, and 1 µF between VCC_IN/OUT and GND.

External TVS diodes may be required for higher transient protection levels. The system designer should ensure that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The device is capable of withstanding up to ±65-V transient pulses < 100 µs.

GUID-E0F1B2FF-4814-4638-9D66-5D3C345B53C5-low.gif
1.2/50 - 80/20 µs CWG
R = 500 Ω
Figure 8-6 Surge Test Setup