JAJSKP0B february 2022 – june 2023 TIOS102 , TIOS1023 , TIOS1025
PRODUCTION DATA
- 1
- 1 特長
- 2 アプリケーション
- 3 概要
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3
Feature Description
- 8.3.1 Current Limit Configuration
- 8.3.2 Current Fault Detection, Indication and Auto Recovery
- 8.3.3 Thermal Warning, Thermal Shutdown
- 8.3.4 Fault Reporting (NFAULT)
- 8.3.5 Device Function Tables
- 8.3.6 The Integrated Voltage Regulator (LDO)
- 8.3.7 Reverse Polarity Protection
- 8.3.8 Integrated Surge Protection and Transient Waveform Tolerance
- 8.3.9 Power Up Sequence
- 8.3.10 Undervoltage Lock-Out (UVLO)
- 8.4 Device Functional Modes
- 9 Application Information Disclaimer
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
- YAH|12
- DRC|10
サーマルパッド・メカニカル・データ
- DRC|10
発注情報
5 Pin Configuration and Functions
Figure 5-1 TIOS1023, TIOS1025 DRC, 10-Pin VSON
(Top View)
Figure 5-2 TIOS102 DRC, 10-Pin VSON
(Top View)
Table 5-1 Pin Functions (VSON Package)
| PIN NO | PIN NAME | Type | DESCRIPTION | |
|---|---|---|---|---|
| TIOS102 | TIOS1023, TIOS1025 | |||
| 1 | VCC_IN | VCC_OUT | P | 3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option without LDO. |
| 2 | NFAULT | NFAULT | O | Fault indicator output signal to the microcontroller. Connect this pin via pull-up resistor to VCC_IN (TIOS102) or VCC_OUT (TIOS1023, TIOS1025) |
| 3 | NC | NC | - | Do not connect to GND. Leave floating |
| 4 | IN | IN | I | Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up. |
| 5 | EN | EN | I | Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-Z. Weak internal pull-down. |
| 6 | ILIM_ADJ | ILIM_ADJ | I | Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND. |
| 7 | GND | GND | GND | Device ground connection |
| 8 | OUT | OUT | O | Driver output |
| 9 | VCC | VCC | P | Supply voltage (24 V nominal) |
| 10 | NC | NC | - | Do not connect to GND. Leave floating |
| Thermal Pad | Thermal Pad | — | Connect to GND plane for optimal thermal and electrical performance | |
Figure 5-3 TIOS1023L YAH, 12-Pin DSBGA
(Top View)
Figure 5-4 TIOS102 YAH, 12-Pin DSBGA
(Top View)
Table 5-2 Pin Functions (DSBGA)
| PIN NO | PIN NAME | Type | DESCRIPTION | |
|---|---|---|---|---|
| TIOS102 | TIOS1023L | |||
| B3 | VCC_IN | VCC_OUT | P | 3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option without LDO. |
| C3 | NFAULT | NFAULT | O | Fault indicator output signal to the microcontroller. Connect this pin via pull-up resistor to VCC_IN (TIOS102) or VCC_OUT (TIOS1023, TIOS1025) |
| D2 | TX | TX | I | Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up. |
| D3 | EN | EN | I | Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-Z. Weak internal pull-down. |
| B1 | ILIM_ADJ | ILIM_ADJ | I | Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND. |
| A1, B2 | GND | GND | GND | Device ground connection |
| A2 | OUT | OUT | O | Switch output |
| A3 | VCC | VCC | P | Supply voltage (24 V nominal) |
| D1, C2 | NC | NC | - | Leave floating. Do not connect. |
| C1 | NC | VSEL | I | TIOS102: Leave floating. Do not connect TIOS1023L: VSEL: Connect to GND for 5V LDO output. Please leave this pin floating for 3.3V LDO output |