JAJSKP0B february 2022 – june 2023 TIOS102 , TIOS1023 , TIOS1025
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLIES (VCC) | |||||||
I(VCC) | Quiescent supply current | EN = LOW, no load | 1 | 1.5 | mA | ||
EN = HIGH, no load | 2.1 | 2.95 | mA | ||||
LOGIC-LEVEL INPUTS (EN, IN, VSEL) | |||||||
VIL | Input logic low voltage | 0.8 | V | ||||
VIH | Input logic high voltage | 2 | V | ||||
RPD | Pull-down (EN) resistance | 100 | kΩ | ||||
RPU | Pull-up (IN) resistance | 200 | kΩ | ||||
RPU | Pull-up (VSEL) resistance | 1000 | kΩ | ||||
CONTROL OUTPUTS (NFAULT) | |||||||
VOL | Output logic low voltage | IO = 4 mA | 0.5 | V | |||
IOZ | Output high impedance leakage | Output in Hi-Z, VO = 0 V or VCC_IN/OUT | –1 | 1 | µA | ||
DRIVER OUTPUT (OUT) | |||||||
RDS(ON) | High-side driver on-resistance | 2.5 | 4.5 | Ω | |||
VDS(ON) | High-side driver residual voltage | I = 200 mA | 0.5 | 0.9 | V | ||
I = 100 mA | 0.25 | 0.5 | V | ||||
RDS(ON) | Low-side driver on-resistance | 2.5 | 4.5 | Ω | |||
VDS(ON) | Low-side driver residual voltage | I = 200 mA | 0.5 | 0.9 | V | ||
I = 100 mA | 0.25 | 0.5 | V | ||||
IPD | OUT pull-down current | EN = LOW, IN = LOW, RSET: >= 10 kΩ | 0 ≤ V(OUT) ≤ (V(VCC) - 0.1) V | 40 | 50 | 80 | µA |
IPU | OUT pull-up current | EN = LOW, IN = HIGH | 40 | 50 | 80 | µA | |
IO(LIM) | Driver output current limit | RSET = 10 kΩ; V(OUT) = (V(VCC)-3) V or 3 V |
300 | 350 | 400 | mA | |
RSET = 110 kΩ; V(OUT) = (V(VCC)-3) V or 3 V |
35 | 50 | 70 | mA | |||
RSET = 0 to 5 kΩ; (3) V(OUT) = (V(VCC)-3) V or 3 V TJ < T(SDN) or t < 200 µs |
500 | mA | |||||
(Fast-detect mode) RSET = OPEN(1) V(OUT) = (V(VCC)-3) V or 3 V |
260 | 330 | 400 | mA | |||
PROTECTION CIRCUITS | |||||||
V(UVLO) | VCC under voltage lockout | VCC falling; NFAULT = Hi-Z | TIOS102 and 3.3V LDO version | 4.2 | 4.4 | V | |
V(UVLO) | VCC under voltage lockout | VCC rising; NFAULT = Hi-Z | 4.6 | 4.75 | V | ||
V(UVLO) | VCC under voltage lockout | VCC falling; NFAULT = Hi-Z | TIOS1025 | 6 | 6.3 | V | |
VCC rising; NFAULT = Hi-Z | 6.5 | 6.8 | V | ||||
V(UVLO,HYS) | VCC under voltage lockout hysteresis | Rising to falling threshold | Rising to falling threshold | 200 | mV | ||
V(UVLO_IN) | VCC_IN under voltage lockout (No LDO option) | VCC_IN falling; NFAULT = Hi-Z | 2.3 | V | |||
VCC_IN rising; NFAULT = LOW | 2.5 | V | |||||
V(UVLO_IN,HYS) | VCC_IN under voltage hysteresis (No LDO option) | Rising to falling threshold | 190 | mV | |||
T(WRN) | Thermal warning | Die temperature TJ | 125 | °C | |||
T(SDN) | Thermal shutdown | 150 | 160 | °C | |||
T(HYS) | Hysteresis for thermal shutdown and warning thresholds | 14 | °C | ||||
IREV | Leakage current in reverse polarity | EN=LOW, IN=x; V(OUT) < V(GND) or V(OUT) > V(VCC), up to |36 V| | 60 | µA | |||
EN=LOW, IN=x; V(OUT) < V(GND) or V(OUT) > V(VCC), up to |55 V| | 110 | µA | |||||
EN = HIGH, IN = LOW; V(OUT to VCC) = 3 V | 640 | µA | |||||
EN = HIGH, IN = HIGH; V(OUT to GND) = -3 V | 10 | µA | |||||
LINEAR REGULATOR (LDO) | |||||||
V(VCC_OUT) | Voltage regulator output | 5 V LDO version | 4.75 | 5 | 5.25 | V | |
3.3 V LDO version | 3.13 | 3.3 | 3.46 | V | |||
V(DROP) | Voltage regulator drop-out voltage (V(VCC) – V(VCC_OUT)) |
ICC = 20 mA load current | 5 V LDO | 1.9 | V | ||
3.3 V LDO | 1.4 | V | |||||
REG | Line regulation (dV(VCC_OUT)/dV(VCC)) | I(VCC_OUT) = 1 mA | 1.7 | mV/V | |||
LREG | Load regulation (dV(VCC_OUT)/V(VCC_OUT)) | V(VCC) = 24 V, I(VCC_OUT) = 100 µA to 20 mA | 1% | ||||
PSSR | Power Supply Rejection Ratio | 100 kHz, I(VCC_OUT) = 20 mA | 40 | dB |