JAJSSZ9I September   2008  – May 2024 TL720M05-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Thermal Shutdown
      3. 7.3.3 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Output Capacitor
        3. 8.1.1.3 New Chip Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
      3. 9.1.3 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • KVU|3
  • PWP|20
  • KTT|3
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

TL720M05-Q1 KTT Package,3-Pin TO-263(Top View)Figure 4-1 KTT Package,3-Pin TO-263(Top View)
TL720M05-Q1 KVU Package,3-Pin TO-252(Top View)Figure 4-2 KVU Package,3-Pin TO-252(Top View)
TL720M05-Q1 PWP Package#GUID-58B3C3DD-3205-4A48-9A5A-777C0F561F2A/SGLS380586,20-Pin HTSSOP With PowerPAD(Top View) Figure 4-3 PWP Package(1),20-Pin HTSSOP With PowerPAD(Top View)
Table 4-1 Pin Functions
PIN TYPE(2) DESCRIPTION
NAME TO-263 TO-252 HTSSOP
(Legacy Chip)
GND 2 2 8 O Ground. Internally connected to heat sink.
IN 1 1 19 I Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground. See the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the input of the device as possible
NC — — 1-3, 5-7, 9-18, 20 — Not connected.
OUT 3 3 4 O Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground. See the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible.
(1) NC = No internal connection.
(2) I = input, O = output.