JAJSSZ9I
September 2008 – May 2024
TL720M05-Q1
PRODMIX
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
Undervoltage Lockout
7.3.2
Thermal Shutdown
7.3.3
Current Limit
7.4
Device Functional Modes
7.4.1
Normal Operation
7.4.2
Dropout Operation
7.4.3
Disabled
8
Application and Implementation
8.1
Application Information
8.1.1
Input and Output Capacitor Selection
8.1.1.1
Legacy Chip Capacitor Selection
8.1.1.2
New Chip Output Capacitor
8.1.1.3
New Chip Input Capacitor
8.1.2
Dropout Voltage
8.1.3
Reverse Current
8.1.4
Power Dissipation (PD)
8.1.4.1
Thermal Performance Versus Copper Area
8.1.4.2
Power Dissipation Versus Ambient Temperature
8.1.5
Estimating Junction Temperature
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input Capacitor
8.2.2.2
Output Capacitor
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Examples
9
Device and Documentation Support
9.1
Device Support
9.1.1
Evaluation Module
9.1.2
Device Nomenclature
9.1.3
Development Support
9.2
Documentation Support
9.2.1
Related Documentation
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
KVU|3
PWP|20
KTT|3
サーマルパッド・メカニカル・データ
PWP|20
PPTD122P
KVU|3
QFND404A
KTT|3
PPTD068B
発注情報
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8.4
Layout