SLVSA96A September 2015 – March 2016 TLC59291
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BLANK | 18 | I | BLANK PIN, has two configures: When FC9(BLANK Mode) = 0, Blank pin worked as SOUT select pin:
When FC9(BLANK Mode) = 1, Blank pin worked as OUTPUT enable pin;
|
GND | 22 | — | Ground |
IREF | 20 | I/O | Maximum current programming terminal. A resistor connected between IREF and GND sets the maximum current for every constant-current output. When this terminal is directly connected to GND, all outputs are forced off. The external resistor should be placed close to the device and must be in the range of 1.32 kΩ to 66 kΩ. |
LAT | 1 | I | Data latch. The rising edge of LAT latches the data from the common shift register into the output on/off data latch. At the same time, the data in the common shift register are replaced with SID, which is selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID) section for more details. |
OUT0 | 2 | O | Constant-current sink outputs. Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. |
OUT1 | 3 | O | |
OUT2 | 4 | O | |
OUT3 | 5 | O | |
OUT4 | 6 | O | |
OUT5 | 7 | O | |
OUT6 | 8 | O | |
OUT7 | 9 | O | |
OUT8 | 10 | O | |
OUT9 | 11 | O | |
OUT10 | 12 | O | |
OUT11 | 13 | O | |
OUT12 | 14 | O | |
OUT13 | 15 | O | |
OUT14 | 16 | O | |
OUT15 | 17 | O | |
SCLK | 24 | I | Serial data shift clock. Data present on SIN are shifted to the LSB of the 16-bit shift register with the SCKI rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of the common shift register appear on SOUT. |
SIN | 23 | I | Serial data input for the 16-bit common shift register. When SIN is high, a '1' is written to the LSB of the common shift register at the rising edge of SCLK. |
SOUT | 19 | O | Serial data output of the 16-bit common shift register. When FC9(BLANK Mode) = 0 and BLANK = LOW; SOUT is connected to the bit 7 of the 16-bit shift register. Data are clocked out at the SCLK rising edge. In other case: SOUT is connected to the bit 15 of the 16-bit shift register. Data are clocked out at the SCLK rising edge. |
VCC | 21 | — | Power-supply voltage |