SLVSCZ9A October   2015  – November 2015 TLC59581 , TLC59582

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Pin Equivalent Input and Output Schematic Diagrams
      1. 8.1.1 Test Circuits
    2. 8.2 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Device Functional Modes
      1. 9.3.1  Brightness Control (BC) Function
      2. 9.3.2  Color Brightness Control (CC) Function
      3. 9.3.3  Select RIREF For a Given BC
      4. 9.3.4  Choosing BC/CC For a Different Application
        1. 9.3.4.1 Example 1: Red LED Current is 20 mA, Green LED Needs 12 mA, Blue LED needs 8 mA
        2. 9.3.4.2 Example 2: Red LED Current is 5 mA, Green LED Needs 2 mA, Blue LED Needs 1 mA.
      5. 9.3.5  LED Open Detection (LOD)
      6. 9.3.6  Internal Circuit for Caterpillar Removal
      7. 9.3.7  Power Save Mode (PSM)
      8. 9.3.8  Internal Pre-Charge FET
      9. 9.3.9  Thermal Shutdown (TSD)
      10. 9.3.10 IREF Resistor Short Protection (ISP)
  10. 10Application and Implementation
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

  1. Place the decoupling capacitor near the VCC pin and GND plane.
  2. Place the current programming resistor RIREF close to IREF pin and IREFGND pin.
  3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is approximately 1.2 A.
  4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as possible to reduce wire inductance.
  5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally, there is a large current flow through this pad when all channels turn on. Furthermore, this pad should be connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via pattern is shown in the Device Layout Example. For more information about suggested thermal via pattern and via size, see PowerPAD Thermally Enhanced Package, SLMA002G.
  6. MOSFETS must be placed in the in the middle of the board, which should be laid out as symmetrically as possible.

12.2 Layout Example

TLC59581 TLC59582 via_layout_SLVSCE7.gif Figure 20. Device Layout Example