JAJSFL0A June 2018 – January 2019 TLC6946 , TLC6948
PRODUCTION DATA.
Place the decoupling capacitor near the VCC pin and GND plane.
Place the current-programming resistor, RIREF, close to the IREF pin and the GND pin.
Make the GND trace as wide as possible for large GND currents.
Routing between the LED cathode and the device OUTn pin must be as short and straight as possible to reduce wire inductance.
The thermal pad (QFN package) must be connected to the GND plane. Because the thermal pad is used as a power ground pin internally, there is a large current flow through this pad when all channels turn on. Furthermore, connect the thermal pad to a heat sink layer by thermal vias to reduce device temperature. One suggested thermal via pattern is shown in Layout Examples. For more information about suggested thermal via pattern and via size, see PowerPAD Thermally Enhanced Package.
MOSFETs must be placed in the in the middle of the board, which should be laid out as symmetrically as possible.