JAJSNK8D November   2021  – July 2022 TLC6984

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Independent and Stackable Mode
        1. 8.3.1.1 Independent Mode
        2. 8.3.1.2 Stackable Mode
      2. 8.3.2 Current Setting
        1. 8.3.2.1 Brightness Control (BC) Function
        2. 8.3.2.2 Color Brightness Control (CC) Function
        3. 8.3.2.3 Choosing BC/CC for a Different Application
      3. 8.3.3 Frequency Multiplier
      4. 8.3.4 Line Transitioning Sequence
      5. 8.3.5 Protections and Diagnostics
        1. 8.3.5.1 Thermal Shutdown Protection
        2. 8.3.5.2 IREF Resistor Short Protection
        3. 8.3.5.3 LED Open Load Detection and Removal
          1. 8.3.5.3.1 LED Open Detection
          2. 8.3.5.3.2 Read LED Open Information
          3. 8.3.5.3.3 LED Open Caterpillar Removal
        4. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 8.3.5.4.1 LED Short and Weak Short Detection
          2. 8.3.5.4.2 Read LED Short Information
          3. 8.3.5.4.3 LSD Caterpillar Removal
    4. 8.4 Device Functional Modes
    5. 8.5 Continuous Clock Series Interface
      1. 8.5.1 Data Validity
      2. 8.5.2 CCSI Frame Format
      3. 8.5.3 Write Command
        1. 8.5.3.1 Chip Index Write Command
        2. 8.5.3.2 VSYNC Write Command
        3. 8.5.3.3 MPSM Write Command
        4. 8.5.3.4 Standby Clear and Enable Command
        5. 8.5.3.5 Soft_Reset Command
        6. 8.5.3.6 Data Write Command
      4. 8.5.4 Read Command
    6. 8.6 PWM Grayscale Control
      1. 8.6.1 Grayscale Data Storage and Display
        1. 8.6.1.1 Memory Structure Overview
        2. 8.6.1.2 Details of Memory Bank
        3. 8.6.1.3 Write a Frame Data into Memory Bank
      2. 8.6.2 PWM Control for Display
    7. 8.7 Register Maps
      1. 8.7.1  FC0
      2. 8.7.2  FC1
      3. 8.7.3  FC2
      4. 8.7.4  FC3
      5. 8.7.5  FC4
      6. 8.7.6  FC14
      7. 8.7.7  FC15
      8. 8.7.8  FC16
      9. 8.7.9  FC17
      10. 8.7.10 FC18
      11. 8.7.11 FC19
      12. 8.7.12 FC20
      13. 8.7.13 FC21
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 System Structure
        2. 9.2.1.2 SCLK Frequency
        3. 9.2.1.3 Internal GCLK Frequency
        4. 9.2.1.4 Line Switch Time
        5. 9.2.1.5 Blank Time Removal
        6. 9.2.1.6 BC and CC
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Chip Index Command
        2. 9.2.2.2 FC Registers Settings
        3. 9.2.2.3 Grayscale Data Write
        4. 9.2.2.4 VSYNC Command
        5. 9.2.2.5 LED Open and Short Read
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VCCDevice supply voltage2.55.5V
VUVRUndervoltage restartVCC rising2.3V
VUVFUndervoltage shutdownVCC falling2.0V
VUV(HYS)Undervoltage shutdown hysteresis0.1V
ICCDevice supply currentSCLK/SIN = 10 MHz, MPSM_EN = 1bit, Matrix PSM enable, internal GCLK off, GSn = 0000h, BC = 2h, CCR/G/B = 63h, PS_EN= 1h, VOUTn = floating, RIREF = 7.8 kΩ (In intelligent power save mode)0.9mA
SCLK/SIN = 10 MHz, Standby enable, internal GCLK off, GSn = 0000h, BC = 2h, CCR/G/B = 63h, PS_EN= 1h, VOUTn = floating, RIREF = 7.8 kΩ (In intelligent power save mode)0.9mA
SCLK/SIN = 10 MHz, PSP_MOD = 1bit, internal GCLK=50MHz, GSn = 0000h, BC = 2h, CCR/G/B = 63h, PS_EN= 1h, VOUTn = floating, RIREF = 7.8 kΩ (In power save mode)3.6mA
SCLK = 10 MHz, internal GCLK = 50 MHz, GSn = 1FFFh, BC = 2h, CCR/G/B = 63h,VOUTn = floating, RIREF = 7.8 kΩ, ICH = 2 mA3.6mA
SCLK = 10 MHz, internal GCLK = 100 MHz, GSn = 1FFFh, BC = 2h, CCR/G/B = 63h, VOUTn = floating, RIREF = 7.8 kΩ, ICH = 2 mA4.9mA
VR/G/BLED supply voltage2.55.5V
VIHHigh level input voltage (SCLK, SIN)0.7 × VCCV
VILLow level input voltage (SCLK, SIN)0.3 × VCCV
VOHHigh level output voltage (SOUT)IOH = –2 mA at SOUTVCC-0.4VCCV
VOLLow level output voltage (SOUT)IOL = 2 mA at SOUT0.4V
ILOGICLogic pin current (SCLK, SIN)SCLK/SIN = VCC or GND-11uA
RDS(ON)Scan switches' on-state resistance (LINE0 to LINE15)VCC = 2.8 V, TA= 25°C190mΩ
VIREFReference voltageSCLK/SIN = GND, internal GCLK= 0MHz, GSn = 0000h, BC = 2h, CCR/G/B = 63h, VOUTn = floating, RIREF = 7.8 kΩ0.8V
VKNEEChannel knee voltage (R0-R15 / G0-G15 / B0-B15)VLEDR/G/B ≥ 2.8 V, all channel outputs on, output current at 1 mA0.25V
VLEDR/G/B ≥ 2.8 V, all channel outputs on, output current at 5 mA0.26V
VLEDR/G/B ≥ 2.8 V, all channel outputs on, output current at 10 mA0.3V
VLEDR/G/B ≥ 2.8 V, IMAX = 1b, all channel outputs on, output current at 15 mA0.37V
VLEDR/G/B ≥ 2.8 V, IMAX=1b, all channel outputs on, output current at 20 mA0.41V
ICH(LKG)Channel leakage current (R0-R15 / G0-G15 / B0-B15)Channel voltage at 0 V1uA
ΔIERR(CC) Constant-current channel to channel deviation (R0-R15 / G0-G15 / B0-B15)(1)All CHn = on, BC = 00h, CC = 31h, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.2-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±1±2.5%
All CHn = on, BC = 00h, CC = 7Dh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±1.5%
All CHn = on, BC = 00h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 1-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±1.5%
All CHn = on, BC = 2h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±2%
All CHn = on, BC = 6h, CC = A7h, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 10-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±2%
All CHn = on, BC = 7h, CC = FBh, IMAX=1b, VOUTn = (VLED-1)V, RIREF = 6.8 kΩ (ICH = 20-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±2.5%
ΔIERR(DD) Constant-current device to device deviation (R0-R15 / G0-G15 / B0-B15)(2)All CHn = on, BC = 00h, CC = 31h, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.2-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±1±2.5%
All CHn = on, BC = 00h, CC = 7Dh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±1.5%
All CHn = on, BC = 00h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 1-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±1%
All CHn = on, BC = 2h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±1.5%
All CHn = on, BC = 6h, CC = A7h, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 10-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±2%
All CHn = on, BC = 7h, CC = FBh, IMAX=1b, VOUTn = (VLED-1)V, RIREF = 6.8 kΩ (ICH = 20-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±0.5±2%
ΔIREG(LINE)Line regulation (R0-R15 / G0-G15 / B0-B15)(3)VLED = 2.5 to 5.5 V, All CHn = on, VOUTn = (VLED-1)V, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±1%/V
ΔIREG(LOAD)Load regulation (R0-R15 / G0-G15 / B0-B15)(4)VOUTn = (VLED-1)V to (VLED-3)V, VR=VG/B=VLED = 3.8 V, All CHn = on, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15±1%/V
TTSDThermal shutdown threshold170°C
THYSThermal shutdown hysteresis15°C
(1) The deviation of each output in same color group (OUTR0-15 or OUTG0-15 or OUTB0-15) from the average of same color group constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0-15) GUID-682E8661-E828-41AB-94F5-D831E13928EE-low.gif

(2) The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) :
GUID-86007FE3-078D-4E50-AC8A-94F672EB7339-low.gif Ideal current is calculated by the following equation: GUID-A3F3025E-DE5E-47D7-9000-3E84156D3499-low.gif

(3) Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
∆ % V = I X n   a t   V L E D = 5.5   V - I X n   a t   V L E D = 2.5   V I X n   a t   V L E D = 2.5   V × 100 5.5   V - 2.5   V
(4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15): ∆%V=IXn at VXn=1 V-IXn at VXn=3 VIXn at VXn=3 V×1003 V-1 V