JAJSC76 May   2016 TLC6C5912

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Thermal Shutdown
      2. 8.3.2 Serial-In Interface
      3. 8.3.3 Clear Register
      4. 8.3.4 Cascade Through SER OUT
      5. 8.3.5 Output Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 3 V
      2. 8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 コミュニティ・リソース
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Logic supply voltage 8 V
VI Logic input-voltage –0.3 8 V
VDS Power DMOS drain-to-source voltage 42 V
Continuous total dissipation See Thermal Information
Operating ambient temperature (Top) 105 °C
TJ Operating junction temperature –40 125 °C
Tstg Storage temperature –55 165 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 3 5.5 V
VIH High-level input voltage 2.4 V
VIL Low-level input voltage 0.7 V
tsu Setup time, SER IN high before SRCK↑ 15 ns
th Hold time, SER IN high after SRCK↑ 15 ns
tw Pulse duration 40 ns
TA Operating ambient temperature –40 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TLC6C5912 UNIT
PW (TSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance 114.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 44.1 °C/W
RθJB Junction-to-board thermal resistance 61.3 °C/W
ψJT Junction-to-top characterization parameter 4.7 °C/W
ψJB Junction-to-board characterization parameter 60.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRAIN0 to DRAIN11,
drain-to-source voltage		 40 V
VOH High-level output voltage,
SER OUT		 IOH = –20 μA VCC = 5 V 4.9 4.99 V
IOH = –4 mA 4.5 4.69
VOL Low-level output voltage,
SER OUT		 IOH = 20 μA VCC = 5 V 0.001 0.01 V
IOH = 4 mA 0.25 0.4
IIH High-level input current VCC = 5 V, VI = VCC 0.2 μA
IIL Low-level input current VCC = 5 V, VI = 0 –0.2 μA
ICC Logic supply current VCC = 5 V,
No clock signal		 All outputs off 0.1 1 μA
All outputs on 130 170
ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz, CL = 30 pF, all outputs on 300 µA
IDSX Off-state drain current VDS = 30 V, VCC = 5 V 0.1 μA
VDS = 30 V, TC = 125°C, VCC = 5 V 0.15 0.3
rDS(on) Static drain-source on-state resistance ID = 20 mA, VCC = 5 V, TA = 25°C, single channel ON 6 7.4 8.6 Ω
ID = 20 mA, VCC = 5 V, TA = 25°C, all channels ON 6.7 8.9 9.6
ID = 20 mA, VCC = 3.3 V, TA = 25°C, single channel ON 7.9 9.3 11.2
ID = 20 mA, VCC = 3.3 V, TA = 25°C, all channels ON 8.7 10.6 12.3
ID = 20 mA, VCC = 5 V, TA = 105°C, single channel ON 9.1 11.2 12.9
ID = 20 mA, VCC = 5 V, TA = 105°C, all channels ON 10.3 13 14.5
ID = 20 mA, VCC = 3.3 V, TA = 105°C, single channel ON 11.6 13.7 16.4
ID = 20 mA, VCC = 3.3 V, TA = 105°C, all channels ON 12.8 15.6 18.2
TSHUTDOWN Thermal shutdown trip point 150 175 200 °C
tHYS Hysteresis 15 °C

6.6 Switching Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from G CL = 30 pF, ID = 48 mA 210 ns
tPHL Propagation delay time, high-to-low-level output from G 75 ns
tr Rise time, drain output 250 ns
tf Fall time, drain output 200 ns
tpd Propagation delay time, SRCK↓ to SEROUT CL = 30 pF, ID = 48 mA 35 ns
tor SEROUT rise time (10% to 90%) CL = 30 pF 20 ns
tof SEROUT fall time (90% to 10%) CL = 30 pF 20 ns
f(SRCK) Serial clock frequency CL = 30 pF, ID = 20 mA 10 MHz
tSRCK_WH SRCK pulse duration, high 30 ns
tSRCK_WL SRCK pulse duration, low 30 ns
TLC6C5912 SER_IN_to_SER_OUT_Waveforms_SLIS141.gif Figure 1. SER IN to SER OUT Waveform

Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 2). As a result, it takes seven and a half periods of SRCK for data to transfer from SER IN to SER OUT.

TLC6C5912 Switching_Times_SLIS141.gif Figure 2. Switching Times and Voltage Waveforms

Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the test circuit shown in Figure 12.

6.7 Typical Characteristics

Conditions for Figure 5 and Figure 6: Single channel on; conditions for Figure 7, Figure 8, and Figure 9: All channels on.
TLC6C5912 D001_SLIS180.gif
VCC = 5 V
Figure 3. Supply Current vs Frequency
TLC6C5912 D003_SLIS180.gif
VCC = 5 V
Figure 5. Drain-to-Source On-State Resistance
vs Drain Current (Single Channel On)
TLC6C5912 D005_SLIS180.gif
VCC = 5 V
Figure 7. Drain-to-Source On-State Resistance
vs Drain Current (All Channels On)
TLC6C5912 D007_SLIS180.gif
I(ds) = 20 mA
Figure 9. Drain-to-Source On-State Resistance
vs Supply Voltage
TLC6C5912 D002_SLIS180.gif
VCC
Figure 4. Supply Current vs Supply Voltage
TLC6C5912 D004_SLIS180.gif
VCC = 3.3 V
Figure 6. Drain-to-Source On-State Resistance
vs Drain Current (Single Channel On)
TLC6C5912 D006_SLIS180.gif
VCC = 3.3 V
Figure 8. Drain-to-Source On-State Resistance
vs Drain Current (All Channels On)
TLC6C5912 D008_SLIS180.gif
Figure 10. Switching Time vs Ambient Temperature