JAJSI77B November   2019  – May 2022 TLIN1028S-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 ABSOLUTE MAXIMUM RATINGS
    2. 7.2 ESD RATINGS
    3. 7.3 ESD RATINGS, IEC SPECIFICATION
    4. 7.4 RECOMMENDED OPERATING CONDITIONS
    5. 7.5 THERMAL INFORMATION
    6. 7.6 POWER SUPPLY CHARACTERISTICS
    7. 7.7 ELECTRICAL CHARACTERISTICS
    8. 7.8 AC SWITCHING CHARACTERISTICS
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuit: Diagrams and Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 LIN Pin
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2 TXD (Transmit Input)
      3. 9.3.3 RXD (Receive Output)
      4. 9.3.4 VSUP (Supply Voltage)
      5. 9.3.5 GND (Ground)
      6. 9.3.6 EN (Enable Input)
      7. 9.3.7 nRST (Reset Output)
      8. 9.3.8 VCC (Supply Output)
      9. 9.3.9 Protection Features
        1. 9.3.9.1 TXD Dominant Time Out (DTO)
        2. 9.3.9.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
        3. 9.3.9.3 Thermal Shutdown
        4. 9.3.9.4 Under Voltage on VSUP
        5. 9.3.9.5 Unpowered Device and LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Wake-Up Request (RXD)
      5. 9.4.5 Mode Transitions
      6. 9.4.6 Voltage Regulator
        1. 9.4.6.1 VCC
        2. 9.4.6.2 Output Capacitance Selection
        3. 9.4.6.3 Low-Voltage Tracking
        4. 9.4.6.4 Power Supply Recommendation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Normal Mode Application Note
        2. 10.2.1.2 TXD Dominant State Timeout Application Note
        3. 10.2.1.3 Brownout
      2. 10.2.2 Detailed Design Procedures
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 ELECTRICAL CHARACTERISTICS

parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RXD OUTPUT TERMINAL (OPEN DRAIN)
VOL Output low voltage Based upon a 2 kΩ to 10 kΩ external pull-up to VCC 0.2 VCC
IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA
ILKG Leakage current, high-level LIN = VSUP, RXD = VCC –5 0 5 µA
TXD INPUT TERMINAL
VIL Low level input voltage –0.3 0.8 V
VIH High level input voltage 2 5.5 V
IIH High level input leakage current TXD = high –5 0 5 µA
RTXD Internal pull-up resistor value 125 350 800 kΩ
LIN TERMINAL (REFERENCED TO VSUP)
VOH HIGH level output voltage LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 36 V 0.85 VSUP
VOL LOW level output voltage LIN dominant, TXD = low, VSUP = 5.5 V to 36 V 0.2 VSUP
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open, VLIN = 5.5 V to 42 V, Bus Load = 60 kΩ + diode and 1.1 kΩ + diode –0.3 42 V
I BUS_LIM Limiting current (ISO/DIS 17987 Param 12) TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V,
VBUSdom < 4.518 V;  Figure 8-5		 40 90 200 mA
I BUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13) VLIN = 0 V, VSUP = 12 V Driver off/recessive, RMEAS = 499 Ω; Figure 8-6 –1 mA
I BUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V Driver off, RMEAS = 1 kΩ;  Figure 8-7 20 µA
I BUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) VLIN = VSUP, Driver off, RMEAS = 1 kΩ; Figure 8-7 –8 8 µA
I BUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15) GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28 V, RMEAS = 1 kΩ;  Figure 8-8 –1 1 mA
IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Param 16) 0 V ≤ VLIN ≤ 28 V, VSUP = GND, RMEAS = 10 kΩ; Figure 8-9 8 µA
VBUSdom Low level input voltage (ISO/DIS 17987 Param 17) LIN dominant (including LIN dominant for wake up);  Figure 8-3, Figure 8-4 0.4 VSUP
VBUSrec High level input voltage (ISO/DIS 17987 Param 18) LIN recessive;  Figure 8-3, Figure 8-4 0.6 VSUP
VBUS_CNT Receiver center threshold (ISO/DIS 17987 Param 19) VBUS_CNT = (VIL + VIH)/2; Figure 8-3, Figure 8-4 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage (ISO/DIS 17987 Param 20) VHYS = (VIL - VIH);  Figure 8-3, Figure 8-4 0.175 VSUP
VSERIAL_DIODE Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21) By design and characterization 0.4 0.7 1.0 V
RRESPONDER Pull-up resistor to VSUP (ISO/DIS 17987 Param 26) Normal and Standby modes 20 45 60 kΩ
IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 12 V, LIN = GND –20 –2 µA
CLIN,PIN Capacitance of the LIN pin 55 pF
EN INPUT TERMINAL
VIH High level input voltage 2 5.5 V
VIL Low level input voltage –0.3 0.8 V
VHYS Hysteresis voltage By design and characterization 30 500 mV
IIL Low level input current EN = Low –5 0 5 µA
REN Internal pull-down resistor 125 350 800 kΩ
ILKG Leakage current, high-level LIN = VSUP, nRST = VCC –5   5 µA
VOL Low-level output voltage Based upon external pull up to VCC     0.2 VCC
IOL Low-level output current, open drain LIN = 0 V, nRST = 0.4 V 1.5   mA
DUTY CYCLE CHARACTERISTICS(1)
D112V Duty Cycle 1 (ISO/DIS 17987 Param 27) THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.396
D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 5.5 V to 18 V,
tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.581
D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.417
D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4 kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11)		 0.59