JAJSO93A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
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When the TLIN1431x-Q1 has certain fault conditions, the device enters a fail-safe mode (FSM). This feature can be disabled in SPI control mode, but is always on in pin control mode. This mode turns on LIMP and brings all other function into lower power mode states. Fault conditions are over-voltage on VCC, thermal shutdown, VCC under-voltage events and reaching restart counter limit in SPI control mode. When entering FSM, a fail-safe mode counter is incremented. The counter limit is set at register 8'h18[7:4], FSM_CNTR_SET and should be set to greater than 1. To avoid unwanted actions the counter should be cleared by writing 0h to 8'h18[3:0]. If the limit is reached a programmed action will be executed, register 8'h17[7:4], FSM_CNTR_ACT. Once the fault conditions are cleared, the device can be put back into restart mode from a wake event. If a fault condition is still in effect after the wake event the device enters sleep. If no wake event takes place, the device enters sleep mode after the programmed SWE timer, tINACT_FS, times out.
Figure 8-42 Fail-safe Mode Pin Control | Figure 8-43 Fail-safe Mode SPI Control |
When the device enters fail-safe mode, the SWE timer automatically starts.
When fail-safe mode is entered due to a thermal shutdown (TSD), VCC over-voltage (OVCC) or a VCC short circuit (VCCSC) event the following takes place:
If the device enters fail-safe mode and VCC is on, the tLDOON timer is started and expires before the device transitions to restart mode.