JAJSK64A
March 2021 – April 2022
TLIN2021A-Q1
PRODMIX
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Pin Configuration and Functions
7
Specification
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
ESD Ratings - IEC Specification
7.4
Thermal Information
7.5
Recommended Operating Conditions
7.6
Power Supply Characteristics
7.7
Electrical Characteristics
7.8
AC Switching Characteristics
7.9
Typical Curves
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
LIN
9.3.1.1
LIN Transmitter Characteristics
9.3.1.2
LIN Receiver Characteristics
9.3.1.2.1
Termination
9.3.2
TXD
9.3.3
RXD
9.3.4
VSUP
9.3.5
GND
9.3.6
EN
9.3.7
WAKE
9.3.8
INH
9.3.9
Local Faults
9.3.10
TXD Dominant Time-Out (DTO)
9.3.11
Bus Stuck Dominant System Fault: False Wake-Up Lockout
9.3.12
Thermal Shutdown
9.3.13
Under Voltage on VSUP
9.3.14
Unpowered Device
9.4
Device Functional Modes
9.4.1
Normal Mode
9.4.2
Sleep Mode
9.4.3
Standby Mode
9.4.4
Wake-Up Events
9.4.4.1
Local Wake-Up (LWU) via WAKE Input Terminal
9.4.4.2
Wake-Up Request (RXD)
10
Application Information Disclaimer
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedures
10.2.2.1
Normal Mode Application Note
10.2.2.2
TXD Dominant State Time-Out Application Note
10.2.2.3
Standby Mode Application Note
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.2
Receiving Notification of Documentation Updates
13.3
サポート・リソース
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
DRB|8
MPDS118K
DDF|8
MPDS569D
サーマルパッド・メカニカル・データ
DRB|8
QFND619
発注情報
jajsk64a_oa
jajsk64a_pm
8
Parameter Measurement Information
Figure 8-1
Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Figure 8-2
RX Response: Operating Voltage Range
Figure 8-3
LIN Bus Input Signal
Figure 8-4
LIN Receiver Test with RX access Param 17, 18, 19, 20
Figure 8-5
V
SUP_NON_OP
Param 11
Figure 8-6
Test Circuit for I
BUS_PAS_dom
; TXD = Recessive State V
BUS
= 0 V, Param 13
Figure 8-7
Test Circuit for I
BUS_PAS_rec
Param 14
Figure 8-8
Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30
Figure 8-9
Definition of Bus Timing Parameters
Figure 8-10
Propagation Delay Test Circuit; Param 31, 32
Figure 8-11
Propagation Delay
Figure 8-12
Mode Transitions
Figure 8-13
Wake-up Through EN
Figure 8-14
Wake-up through LIN