JAJSEB1D December   2017  – June 2022 TLIN2022-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC
    4. 6.4 Thermal Information
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics (1)
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  LIN (Local Interconnect Network) Bus
        1. 7.3.1.1 LIN Transmitter Characteristics
        2. 7.3.1.2 LIN Receiver Characteristics
          1. 7.3.1.2.1 Termination
      2. 7.3.2  TXD (Transmit Input and Output)
      3. 7.3.3  RXD (Receive Output)
      4. 7.3.4  VSUP (Supply Voltage)
      5. 7.3.5  GND (Ground)
      6. 7.3.6  EN (Enable Input)
      7. 7.3.7  Protection Features
      8. 7.3.8  TXD Dominant Time Out (DTO)
      9. 7.3.9  Bus Stuck Dominant System Fault: False Wake Up Lockout
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Under Voltage on VSUP
      12. 7.3.12 Unpowered Device and LIN Bus
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Wake Up Events
        1. 7.4.4.1 Wake Up Request (RXD)
        2. 7.4.4.2 Mode Transitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Normal Mode Application Note
        2. 8.2.2.2 Standby Mode Application Note
        3. 8.2.2.3 TXD Dominant State Timeout Application Note
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1 Design Requirements

The RXD output structure is an open-drain output stage. This allows the TLIN2022-Q1 to be used with 3.3-V and 5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be between 1 kΩ to 10 kΩ. The VSUP pin of the device should be decoupled with a 100 nF capacitor as close to the supply pin of the device as possible. The system should include 1 µF and ≥ 10 µF decoupling capacitors on VSUP as per each application requirements.