JAJSKO1 データシート

JAJSKO1M December 2004 – January 2023 TLV1117

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

KVU|3
DRJ|8
DCY|4
KCS|3
KTT|3
KCT|3

サーマルパッド・メカニカル・データ

KVU|3
- QFND404A
KTT|3
- PPTD068B
DRJ|8
- QFND085E
DCY|4
- QFND222B

発注情報

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾⁽³⁾		TLV1117							UNITS
		PowerFlex		DRJ (8 PINS)	DCY (4 PINS)	KVU (3 PINS)	KCS, KCT (3 PINS)	KTT (3 PINS)
		KTE (3 PINS)	KTP (3 PINS)	DRJ (8 PINS)	DCY (4 PINS)	KVU (3 PINS)	KCS, KCT (3 PINS)	KTT (3 PINS)
R_θJA	Junction-to-ambient thermal resistance	38.6	49.2	38.3	104.3	50.9	30.1	27.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	34.7	60.6	36.5	53.7	57.9	44.6	43.2	°C/W
R_θJB	Junction-to-board thermal resistance	3.2	3.1	60.5	5.7	34.8	1.2	17.3	°C/W
ψ_JT	Junction-to-top characterization parameter	5.9	8.7	0.2	3.1	6	5	2.8	°C/W
ψ_JB	Junction-to-board characterization parameter	3.1	3	12	5.5	23.7	1.2	9.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3	3	4.7	n/a	0.4	0.4	0.3	°C/W
R_θJP	Thermal resistance between the die junction and the bottom of the exposed pad.	2.7	1.4	1.78	n/a	n/a	3	1.94	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.