SBOS589D December   2013  – June 2015 TLV1701 , TLV1702 , TLV1704

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TLV1701
    5. 7.5 Thermal Information: TLV1702 and TLV1704
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Comparator Inputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Reference Voltage
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage +40 (±20) V
Signal input pins Voltage(2) (VS–) – 0.5 (VS+) + 0.5 V
Current(2) ±10 mA
Output short-circuit(3) Continuous mA
Operating temperature range –55 +150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 +150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground; one comparator per package.

7.2 ESD Ratings

VALUE UNIT
TLV1701 and TLV1702
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
TLV1704
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage VS = (VS+) – (VS–) 2.2 (±1.1) 36 (±18) V
Specified temperature –40 125 °C

7.4 Thermal Information: TLV1701

THERMAL METRIC(1) TLV1701 UNIT
DRL (SOT553) DCK (SC70) DBV (SOT23)
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 271.5 283.6 233.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 115.6 94.1 156.4 °C/W
RθJB Junction-to-board thermal resistance 89.7 61.3 60.6 °C/W
ψJT Junction-to-top characterization parameter 17.6 1.9 35.7 °C/W
ψJB Junction-to-board characterization parameter 89.2 60.5 59.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Thermal Information: TLV1702 and TLV1704

THERMAL METRIC(1) TLV1702 TLV1704 UNIT
RUG (QFN) DGK (VSSOP) PW (TSSOP)
8 PINS 8 PINS 14 PINS
θJA Junction-to-ambient thermal resistance 205.6 199 128.1 °C/W
θJCtop Junction-to-case (top) thermal resistance 77.1 89.5 56.5 °C/W
θJB Junction-to-board thermal resistance 107.0 120.4 69.9 °C/W
ψJT Junction-to-top characterization parameter 2.0 22.0 9.1 °C/W
ψJB Junction-to-board characterization parameter 107.0 118.7 69.3 °C/W
θJCbot Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W

7.6 Electrical Characteristics

at TA = +25°C, VS = +2.2 V to +36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage TA = 25°C, VS = 2.2 V ±0.5 ±3.5 mV
TA = 25°C, VS = 36 V ±0.3 ±2.5 mV
TA = –40°C to +125°C ±5.5 mV
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±4 ±20 μV/°C
PSRR Power-supply rejection ratio 15 100 μV/V
TA = –40°C to +125°C 20 μV/V
INPUT VOLTAGE RANGE
VCM Common-mode voltage range TA = –40°C to +125°C (V–) (V+) V
INPUT BIAS CURRENT
IB Input bias current 5 15 nA
TA = –40°C to +125°C 20 nA
IOS Input offset current 0.5 nA
CLOAD Capacitive load drive See Typical Characteristics
OUTPUT
VO Voltage output swing from rail IO ≤ 4 mA, input overdrive = 100 mV,
VS = 36 V		 900 mV
IO = 0 mA, input overdrive = 100 mV,
VS = 36 V		 600 mV
ISC Short circuit sink current 20 mA
Output leakage current VIN+ > VIN– 70 nA
POWER SUPPLY
VS Specified voltage range 2.2 36 V
IQ Quiescent current (per channel) IO = 0 A 55 75 μA
IO = 0 A, TA = –40°C to +125°C 100 μA

7.7 Switching Characteristics

at TA = +25°C, VS = +2.2 V to +36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpHL Propagation delay time, high-to-low Input overdrive = 100 mV 460 ns
tpLH Propagation delay time, low-to-high Input overdrive = 100 mV 560 ns
tR Rise time Input overdrive = 100 mV 365 ns
tF Fall time Input overdrive = 100 mV 240 ns

7.8 Typical Characteristics

at TA = +25°C, VS = +5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
TLV1701 TLV1702 TLV1704 C017_SBOS589.png
Figure 1. Quiescent Current vs Temperature
TLV1701 TLV1702 TLV1704 C014_SBOS589.png
Figure 3. Input Offset Current vs Temperature
TLV1701 TLV1702 TLV1704 C003_SBOS589.png
Figure 5. Offset Voltage vs Common-Mode Voltage
TLV1701 TLV1702 TLV1704 C001_SBOS589.png
Figure 7. Offset Voltage vs Supply Voltage
TLV1701 TLV1702 TLV1704 C006_SBOS589.png
Figure 9. Propagation Delay vs Capacitive Load
TLV1701 TLV1702 TLV1704 C007_SBOS589.png
Figure 11. Propagation Delay (TpLH)
TLV1701 TLV1702 TLV1704 C009_SBOS589.png
Figure 13. Propagation Delay (TpLH)
TLV1701 TLV1702 TLV1704 C005_SBOS589.png
Figure 15. Offset Voltage Production Distribution
TLV1701 TLV1702 TLV1704 C016_SBOS589.png
Figure 17. Short-Circuit Current vs Supply Voltage
TLV1701 TLV1702 TLV1704 C015_SBOS589.png
Figure 2. Input Bias Current vs Temperature
TLV1701 TLV1702 TLV1704 C011_SBOS589.png
Figure 4. Output Voltage vs Output Current
TLV1701 TLV1702 TLV1704 C002_SBOS589.png
Figure 6. Offset Voltage vs Common-Mode Voltage
TLV1701 TLV1702 TLV1704 C013_SBOS589.png
Figure 8. Propagation Delay vs Input Overdrive
TLV1701 TLV1702 TLV1704 C012_SBOS589.png
Figure 10. Propagation Delay vs Temperature
TLV1701 TLV1702 TLV1704 C008_SBOS589.png
Figure 12. Propagation Delay (TpHL)
TLV1701 TLV1702 TLV1704 C010_SBOS589.png
Figure 14. Propagation Delay (TpHL)
TLV1701 TLV1702 TLV1704 C004_SBOS589.png
Figure 16. Offset Voltage Production Distribution