JAJSNH6 august   2023 TLV1851-Q1 , TLV1861-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Configuration: TLV1851-Q1 and TLV1861-Q1
    2.     Pin Configurations: TLV1852-Q1 and TLV1862-Q1
    3.     Pin Configurations: TLV1854-Q1 and TLV1864-Q1
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
        1. 7.4.1.1 Operating Common-Mode Ranges
        2. 7.4.1.2 Fail-Safe Inputs
        3. 7.4.1.3 Unused Inputs
      2. 7.4.2 Internal Hysteresis
      3. 7.4.3 Outputs
        1. 7.4.3.1 TLV185x-Q1 Push-Pull Output
        2. 7.4.3.2 TLV186x-Q1 Open-Drain Output
      4. 7.4.4 ESD Protection
        1. 7.4.4.1 Inputs
        2. 7.4.4.2 Outputs
      5. 7.4.5 Power-On Reset (POR)
      6. 7.4.6 Reverse Battery Protection
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Comparator Definitions
        1. 8.1.1.1 Operation
        2. 8.1.1.2 Propagation Delay
        3. 8.1.1.3 Overdrive Voltage
      2. 8.1.2 Hysteresis
        1. 8.1.2.1 Inverting Comparator With Hysteresis
        2. 8.1.2.2 Non-Inverting Comparator With Hysteresis
        3. 8.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
    2. 8.2 Typical Applications
      1. 8.2.1 Window Comparator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Undervoltage Detection
      3. 8.2.3 Reverse Battery and Overvoltage Protection Scheme
    3. 8.3 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.3.2 TLV186x-Q1 Open-Drain Output

The TLV186x-Q1 features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage from 0 V up to 40 V, independent of the comparator supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic level translation. TI recommends setting the pull-up resistor current to less than 100 uA to optimize VOL logic levels. Lower pull-up resistor values will help increase the rising edge risetime, but at the expense of increasing VOL and higher power dissipation. The risetime will be dependent on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the output RC time constant and increase the risetime.

Directly shorting the output to (V+) can result in thermal runaway and eventual device destruction at high (>12 V) pull-up voltages. If output shorts are possible, a series current limitng resistor is recommended to limit the power dissipation.

Unused open drain outputs should be left floating, or can be tied to the (V-) pin if floating pins are not desired.