SNOSDG0 August   2024 TLV1H103-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
      2. 6.4.2 Push-Pull (Single-Ended) Output
      3. 6.4.3 Known Startup Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Hysteresis
      2. 7.1.2 Capacitive Loads
      3. 7.1.3 Latch Functionality
    2. 7.2 Typical Application
      1. 7.2.1 Implementing Adjustable Hystseresis
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Optical Receiver
      3. 7.2.3 Over-Current Latch Condition
      4. 7.2.4 External Trigger Function
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.1 Layout Guidelines

Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.

  1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding (use of a ground plane) helps maintain specified device performance.

    Likewise, high performance board materials such as Rogers or high speed FR4 is also recommended.

  2. Place a decoupling capacitor (100pF ceramic, surface-mount capacitor) between VCC and

    VEE as close to the device as possible. Using multiple bypass capacitors in different decade ranges such as 100pF, 100nF, and 1µF provides the best noise reduction across frequency ranges.

  3. On the inputs and the output, keep lead lengths as short and minimize capacitive coupling to the traces by having a keepout area around the traces that is 3x the width of the traces. Also recommended is to keep input traces away from the output traces.
  4. Solder the device directly to the PCB rather than using a socket.