When the design is required to detect a brief over-current condition, the latching feature of the TLV1H103-SEP can be utilized. By latching the comparator output, the MCU does not miss the over-current occurrence. The circuit below shows one way to implement the latching function.

When an over-current condition is detected by the TLV1H103-SEP, the output transitions high. The occurrence of the output going high coupled with a logic high from the RESET signal from the MCU creates a logic low signal at the output of the 2-channel NAND gate. This causees the output of the TLV1H103-SEP to be held in a logic high state (latched), thus allowing the MCU to detect the fault condition regardless of how narrow the over-current condition persists. The addition of the NAND gate also provides a means of clearing the latch state of the comparator once the MCU is done processing the event. This is accomplished by the MCU passing a logic low state to the NAND input causing the LE/HYS pin of the comparator to be returned to a logic high state. The latched status is cleared and the TLV1H103-SEP output can continue to track the status of the input pins.

Over-Current Latched Output Circuit