36V TLVx171ファミリは、省コストが重要な産業用や個人用電子機器システム向けの低消費電力オペアンプ(op amp)で、電磁気干渉(EMI)耐性が高く、低ノイズで、2.7V (±1.35V)~36 V (±18V)の単一電源で動作します。1チャネルのTLV171、2チャネルのTLV2171、4チャネルのTLV4171があり、消費電力制限の中で、低いオフセット、ドリフト係数、静止電流と、高い帯域幅との最適なバランスを実現しています。これらのデバイスは、容積の制限が厳しいシステム用にマイクロパッケージで供給され、仕様が同一なので、設計を最大に柔軟化できます。
ほとんどのオペアンプでは1つの電源電圧でしか動作が規定されていないのに対して、TLVx171ファミリは2.7V~36Vでの動作が規定されています。電源レールの範囲外の入力信号が位相反転を起こすことはありません。TLVx171ファミリは、最大200pFの容量性負荷で安定です。通常の動作時に、入力は負のレールより100mV下、および上限レールの2V以内で動作できます。これらのデバイスは完全なレール・ツー・レール入力で、上限レールを100mV超えて動作し、上限レールの2V以内ではパフォーマンスが低下して動作します。
TLVx171オペアンプは、-40℃~+125℃での動作が規定されています。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
TLV171 | SOIC (8) | 4.90mm×3.91mm |
SOT-23 (5) | 2.90mm×1.60mm | |
TLV2171 | SOIC (8) | 4.90mm×3.91mm |
VSSOP (8) | 3.00mm×3.00mm | |
TLV4171 | SOIC (14) | 8.65mm×3.91mm |
TSSOP (14) | 5.00mm×4.40mm |
日付 | 改訂内容 | 注 |
---|---|---|
2016年9月 | * | 初版 |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | TLV171 | |||
DBV | D | |||
IN– | 4 | 2 | I | Negative (inverting) input |
IN+ | 3 | 3 | I | Positive (noninverting) input |
NC(1) | — | 1, 5, 8 | — | No internal connection (can be left floating) |
OUT | 1 | 6 | O | Output |
V+ | 5 | 7 | — | Positive (highest) power supply |
V– | 2 | 4 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | TLV2171 | |||
D | DGK | |||
–IN A | 2 | 2 | I | Inverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
+IN A | 3 | 3 | I | Noninverting input, channel A |
+IN B | 5 | 5 | I | Noninverting input, channel B |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 8 | 8 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | D | PW | ||
–IN A | 2 | 2 | I | Inverting input, channel A |
+IN A | 3 | 3 | I | Noninverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
+IN B | 5 | 5 | I | Noninverting input, channel B |
–IN C | 9 | 9 | I | Inverting input, channel C |
+IN C | 10 | 10 | I | Noninverting input, channel C |
–IN D | 13 | 13 | I | Inverting input, channel D |
+IN D | 12 | 12 | I | Noninverting input, channel D |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
OUT C | 8 | 8 | O | Output, channel C |
OUT D | 14 | 14 | O | Output, channel D |
V– | 11 | 11 | — | Negative (lowest) power supply |
V+ | 4 | 4 | — | Positive (highest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply voltage, V+ to V− | –20 | 20 | V |
Signal input pin | (V−) − 0.5 | (V+) + 0.5 | ||
Current | Signal input pin | –10 | 10 | mA |
Output short-circuit(2) | Continuous | |||
Temperature | Operating, TA | –55 | 150 | °C |
Junction, TJ | 150 | |||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage (V+ – V–) | Single supply | 2.7 | 36 | V | |
Dual supply | ±1.35 | ±18 | |||
Specified temperature | –40 | +125 | °C |
THERMAL METRIC(1) | TLV171 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DBV (SOT-23) | |||
8 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 149.5 | 245.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 97.9 | 133.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 87.7 | 83.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 35.5 | 18.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 89.5 | 83.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | TLV2171 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 134.3 | 175.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 72.1 | 74.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 60.6 | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 18.2 | 1.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 53.8 | 22.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | TLV4171 | UNIT | ||
---|---|---|---|---|
D (SOIC) | PW (TSSOP) | |||
14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 93.2 | 106.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.8 | 24.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 49.4 | 59.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 13.5 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 42.2 | 54.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||
VOS | Input offset voltage | TA = 25°C | 0.75 | ±2.7 | mV | |
TA = –40°C to +125°C | ±3.0 | |||||
dVOS/dT | Input offset voltage drift | TA = –40°C to +125°C | 1 | µV/°C | ||
PSRR | Input offset voltage vs power supply | VS = 4 V to 36 V, TA = –40°C to +125°C | 90 | 105 | dB | |
INPUT BIAS CURRENT | ||||||
IB | Input bias current | ±10 | pA | |||
IOS | Input offset current | ±4 | pA | |||
NOISE | ||||||
Input voltage noise | f = 0.1 Hz to 10 Hz | 3 | µVPP | |||
en | Input voltage noise density | f = 100 Hz | 27 | nV/√Hz | ||
f = 1 kHz | 16 | |||||
INPUT VOLTAGE | ||||||
VCM | Common-mode voltage range(1) | (V–) – 0.1 | (V+) – 2 | V | ||
CMRR | Common-mode rejection ratio | VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V, TA = –40°C to +125°C |
94 | 105 | dB | |
INPUT IMPEDANCE | ||||||
Differential | 100 || 3 | MΩ || pF | ||||
Common-mode | 6 || 3 | 1012 Ω || pF | ||||
OPEN-LOOP GAIN | ||||||
AOL | Open-loop voltage gain | VS = 36 V, (V–) + 0.35 V < VO < (V+) – 0.35 V, TA = –40°C to +125°C |
94 | 130 | dB | |
FREQUENCY RESPONSE | ||||||
GBP | Gain bandwidth product | 3.0 | MHz | |||
SR | Slew rate | G = +1 | 1.5 | V/µs | ||
tS | Settling time | To 0.1%, VS = ±18 V, G = +1, 10-V step | 6 | µs | ||
To 0.01% (12 bits), VS = ±18 V, G = +1, 10-V step |
10 | |||||
Overload recovery time | VIN × gain > VS | 2 | µs | |||
THD+N | Total harmonic distortion + noise | G = +1, f = 1 kHz, VO = 3 VRMS | 0.0002% | |||
OUTPUT | ||||||
VO | Voltage output swing | Positive rail, VS = ±18 V, RL = 10 kΩ, TA = 25°C |
160 | mV | ||
Negative rail, VS = ±18 V, RL = 10 kΩ, TA = 25°C |
90 | mV | ||||
RL = 10 kΩ, AOL ≥ 94 dB, TA = –40°C to +125°C |
(V–) + 0.35 | (V+) – 0.35 | V | |||
ISC | Short-circuit current | 25 | mA | |||
–35 | ||||||
CLOAD | Capacitive load drive | See Typical Characteristics | pF | |||
RO | Open-loop output resistance | f = 1 MHz, IO = 0 A | 150 | Ω | ||
POWER SUPPLY | ||||||
VS | Specified voltage range | 2.7 | 36 | V | ||
IQ | Quiescent current per amplifier | IO = 0 A, TA = –40°C to +125°C | 525 | 695 | µA | |
TEMPERATURE | ||||||
Specified range | –40 | 125 | °C | |||
Operating range | –55 | 150 | °C |
DESCRIPTION | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 1 |
Offset Voltage vs Common-Mode Voltage | Figure 2 |
Offset Voltage vs Common-Mode Voltage (Upper Stage) | Figure 3 |
Input Bias Current and Input Offset Current vs Temperature | Figure 4 |
Output Voltage Swing vs Output Current (Maximum Supply) | Figure 5 |
CMRR and PSRR vs Frequency (Referred-to-Input) | Figure 6 |
0.1-Hz to 10-Hz Noise | Figure 7 |
Input Voltage Noise Spectral Density vs Frequency | Figure 8 |
Quiescent Current vs Supply Voltage | Figure 9 |
Open-Loop Gain and Phase vs Frequency | Figure 10 |
Closed-Loop Gain vs Frequency | Figure 11 |
Open-Loop Gain vs Temperature | Figure 12 |
Open-Loop Output Impedance vs Frequency | Figure 13 |
Small-Signal Overshoot vs Capacitive Load | Figure 14, Figure 15 |
No Phase Reversal | Figure 16 |
Small-Signal Step Response (100 mV) | Figure 17, Figure 18 |
Large-Signal Step Response | Figure 19, Figure 20 |
Large-Signal Settling Time (10-V Positive Step) | Figure 21 |
Large-Signal Settling Time (10-V Negative Step) | Figure 22 |
Short-Circuit Current vs Temperature | Figure 23 |
Maximum Output Voltage vs Frequency | Figure 24 |
EMIRR IN+ vs Frequency | Figure 25 |
Distribution taken from 3500 amplifiers |
10 typical units shown |
100-mV output step, RL = 10 kΩ |
RL = 10 kΩ, CL = 100 pF |
G = +1, RL = 10 kΩ, CL = 100 pF |
10-V positive step, G = –1 |
10 typical units shown |
5 typical units shown |
100-mV output step, RL = 10 kΩ |
G = –1, RL = 10 kΩ, CL = 100 pF |
10-V negative step, G = –1 |