JAJSF41 March 2018 TLV320ADC3100
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
AUDIO ADC | |||||||
Input signal level (0-dB) | Single-ended input | 0.707 | Vrms | ||||
Input common-mode voltage | Single-ended input | 1.35 | Vrms | ||||
SNR | Signal-to-noise ratio,
A-weighted(1)(2) |
fS = 48 kHz, 0-dB PGA gain, IN1 inputs selected
and AC-shorted to ground |
80 | 92 | dB | ||
Dynamic range,
A-weighted(1)(2) |
fS = 48 kHz; 1-kHz, –60-dB, full-scale input applied at IN1 inputs; 0-dB PGA gain | 92 | dB | ||||
THD | Total harmonic distortion | fS = 48 kHz; 1-kHz, –2-dB, full-scale input applied at IN1 inputs; 0-dB PGA gain | –90 | –75 | dB | ||
0.003% | 0.017% | ||||||
PSRR | Power-supply rejection ratio | 234 Hz, 100 mVPP on AVDD, single-ended input | 46 | dB | |||
234 Hz, 100 mVPP on AVDD, differential input | 68 | ||||||
ADC channel separation | 1 kHz, –2-dB IN2L to IN2R | –73 | dB | ||||
ADC gain error | 1 kHz input, 0-dB PGA gain | 0.7 | dB | ||||
ADC programmable-gain amplifier maximum gain | 1-kHz input tone, RSOURCE < 50 Ω | 40 | dB | ||||
ADC programmable-gain amplifier step size | 0.502 | dB | |||||
Input resistance | IN1 inputs, routed to single ADC,
input mix attenuation = 0 dB |
35 | kΩ | ||||
IN2 inputs, input mix attenuation = 0 dB | 35 | ||||||
IN1 inputs, input mix attenuation = –6 dB | 62.5 | ||||||
IN2 inputs, input mix attenuation = –6 dB | 62.5 | ||||||
Input capacitance | 10 | pF | |||||
Input level control minimum attenuation setting | 0 | dB | |||||
Input level control maximum attenuation setting | 6 | dB | |||||
Input level control attenuation step size | 6 | dB | |||||
ADC DIGITAL DECIMATION FILTER (fS = 48 kHz) | |||||||
Filter gain from 0 fS to 0.39 fS | Filter A, AOSR = 128 or 64 | ±0.1 | dB | ||||
Filter gain from 0.55 fS to 64 fS | Filter A, AOSR = 128 or 64 | –73 | dB | ||||
Filter group delay | Filter A, AOSR = 128 or 64 | 17 / fS | s | ||||
Filter gain from 0 fS to 0.39 fS | Filter B, AOSR = 64 | ±0.1 | dB | ||||
Filter gain from 0.60 fS to 32 fS | Filter B, AOSR = 64 | –46 | dB | ||||
Filter group delay | Filter B, AOSR = 64 | 11 / fS | s | ||||
Filter gain from 0 fS to 0.39 fS | Filter C, AOSR = 32 | ±0.033 | dB | ||||
Filter gain from 0.28 fS to 16 fS | Filter C, AOSR = 32 | –60 | dB | ||||
Filter group delay | Filter C, AOSR = 32 | 11 / fS | s | ||||
MICROPHONE BIAS | |||||||
Bias voltage | Programmable settings, load = 750 Ω | 2 | V | ||||
2.25 | 2.5 | 2.75 | |||||
AVDD – 0.2 | |||||||
Current sourcing | 2.5-V setting | 4 | mA | ||||
Integrated noise | BW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AGND | 3.3 | µV
rms |
||||
DIGITAL I/O | |||||||
VIL | Input low level | IIL = 5 µA | –0.3 | 0.3 × IOVDD | V | ||
VIH | Input high level(3) | IIH = 5 µA | 0.7 × IOVDD | V | |||
VOL | Output low level | IIH = 2 TTL loads | 0.1 × IOVDD | V | |||
VOH | Output high level | IOH = 2 TTL loads | 0.8 × IOVDD | V | |||
SUPPLY CURRENT (fS = 48 kHz, AVDD = 3.3 V, DVDD = IOVDD = 1.8 V) | |||||||
Mono record | AVDD | PLL and AGC off | 2 | mA | |||
DVDD | 1.9 | ||||||
Stereo record | AVDD | PLL and AGC off | 4 | mA | |||
DVDD | 2.1 | ||||||
PLL | AVDD | Additional power consumed when PLL is powered | 1.1 | mA | |||
DVDD | 0.8 | ||||||
Power down | AVDD | All supply voltages applied, all blocks programmed in lowest power state | 0.04 | µA | |||
DVDD | 0.7 |