JAJSF41 March 2018 TLV320ADC3100
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NADC CLK PWR | NADC CLK DIV | ||||||
R/W-0h | R/W-000 0001h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | NADC CLK PWR | R/W | 0h | NADC clock divider power control:
0: NADC clock divider is powered down 1: NADC clock divider is powered up |
6:0 | NADC CLK DIV | R/W | 000 0001h | NADC value:
000 0000: NADC clock divider = 128 000 0001: NADC clock divider = 1 000 0010: NADC clock divider = 2 ... 111 1110: NADC clock divider = 126 111 1111: NADC clock divider = 127 |