JAJSF41 March 2018 TLV320ADC3100
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADC CLK PWR | MADC CLK DIV | ||||||
R/W-0h | R/W-000 0001h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MADC CLK PWR | R/W | 0h | 0: ADC MADC clock divider is powered down
1: ADC MADC clock divider is powered up |
6:0 | MADC CLK DIV | R/W | 000 0001h | 000 0000: MADC clock divider = 128
000 0001: MADC clock divider = 1 000 0010: MADC clock divider = 2 ... 111 1110: MADC clock divider = 126 111 1111: MADC clock divider = 127 |