JAJSL95G March   2007  – February 2021 TLV320AIC3104

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Audio Data Serial Interface Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
      4. 10.3.4  Stereo Audio DAC
        1. 10.3.4.1 Digital Audio Processing for Playback
        2. 10.3.4.2 Digital Interpolation Filter
        3. 10.3.4.3 Delta-Sigma Audio DAC
        4. 10.3.4.4 Audio DAC Digital Volume Control
        5. 10.3.4.5 Increasing DAC Dynamic Range
        6. 10.3.4.6 Analog Output Common-Mode Adjustment
        7. 10.3.4.7 Audio DAC Power Control
      5. 10.3.5  Audio Analog Inputs
      6. 10.3.6  Analog Fully Differential Line Output Drivers
      7. 10.3.7  Analog High-Power Output Drivers
      8. 10.3.8  Input Impedance and VCM Control
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Short-Circuit Output Protection
      11. 10.3.11 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 ADC PGA Signal Bypass Path Functionality
        2. 10.4.1.2 Passive Analog Bypass During Power Down
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Interface
        1. 10.5.1.1 I2C Bus Debug in a Glitched System
      2. 10.5.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Typical Connections With Headphone and External Speaker Driver in Portable Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curves
      2. 11.2.2 Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 ドキュメントの更新通知を受け取る方法
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 静電気放電に関する注意事項
    5. 14.5 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
サーマルパッド・メカニカル・データ
発注情報

10.3.3.1 Audio Clock Generation

The audio converters in the TLV320AIC3104 need an internal audio master clock at a frequency of 256 fS(ref), which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC3104 is shown in Figure 10-8.

GUID-84B3F555-2C82-4170-9101-7C3A29B4D3ED-low.gifFigure 10-8 Audio Clock Generation Processing

The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled,

Equation 1. fS(ref) = CLKDIV_IN / (128 × Q)

where

  • Q = 2, 3, …, 17. Q is register programmable and can be set in page 0, register 3, bits D6–D3.

CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6.

Note:

In the absence of an MCLK, CLKDIV_IN must receive an active clock for proper functionality. For three-wire I2S, when BCLK is selected for PLL_IN (page 0, register 102), BCLK must also be selected for CLKDIV_IN.

NOTE – when NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz, inclusive.

When the PLL is enabled,

Equation 2. fS(ref) = (PLLCLK_IN × K × R) / (2048 × P)

where

  • P = 1, 2, 3,…, 8
  • R = 1, 2, …, 16
  • K = J.D
  • J = 1, 2, 3, …, 63
  • D = 0000, 0001, 0002, 0003, …, 9998, 9999
  • PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5–D4

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision). P can be set in page 0, register 3, bits D2–D0. R can be set in page 0, register 11, bits D3–D0. J can be set in page 0, register 4, bits D7–D2. The most-significant bits of D can be set in page 0, register 5, bits D7–D0, and the least-significant bits of D can be set in page 0, register 6, bits D7–D2.

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

512 kHz ≤ (PLLCLK_IN/P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R/P) ≤ 110 MHz
4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Example:

MCLK = 12 MHz and fS(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and fS(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Table 10-1 lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1 kHz or 48 kHz.

Table 10-1 Typical MCLK Rates
MCLK (MHz)PRJDACHIEVED fS(ref)% ERROR
fS(ref) = 44.1 kHz
2.82241132   044,100   0
5.64481116   044,100   0
1211 7526444,100   0
1311 6947444,099.71–0.0007
1611 5644844,100   0
19.211 4704044,100   0
19.6811 4589344,100.3  0.0007
4841 7526444,100   0
fS(ref) = 48 kHz
2.0481148   048,000   0
3.0721132   048,000   0
4.0961124   048,000   0
6.1441116   048,000   0
8.1921112   048,000   0
1211 8192048,000   0
1311 7561847,999.71–0.0006
1611 6144048,000   0
19.211 5120048,000   0
19.6811 4995147,999.79–0.0004
4841 8192048,000   0