JAJSDO3 データシート

JAJSDO3A August 2017 – November 2017 TLV320AIC3109-Q1

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RHB|32
- MPQF130D
RHM|32
- MPQF152B

サーマルパッド・メカニカル・データ

RHB|32
- QFND029X
RHM|32
- QFND568

発注情報

6 Specifications

6.1 Absolute Maximum Ratings

⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Power-supply voltage	AVDD to AVSS, DRVDD to DRVSS	–0.3	3.9	V
	AVDD to DRVSS	–0.3	3.9
	IOVDD to DVSS	–0.3	3.9
	DVDD to DVSS	–0.3	2.5
	AVDD to DRVDD	–0.1	0.1
Analog input voltage	Analog input voltage to AVSS	–0.3	AVDD + 0.3	V
Digital input voltage	Digital input voltage to DVSS	–0.3	IOVDD + 0.3	V
Temperature	Operating ambient, T_A	–40	105	°C
	Junction, T_J	–40	125
	Storage, T_stg	–40	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) ESD compliance tested to EIA/JESD22-A114-B and passed.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±2000	V
		Charged-device model (CDM), per AEC Q100-011	Corner pins (1, 8, 9, 16,17, 24, 25, 32)	±750
		Charged-device model (CDM), per AEC Q100-011	All other pins	±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
POWER SUPPLY
	Analog supply voltage (AVDD to AVSS, DRVDD to DRVSS)	2.7	3.3	3.6	V
	Digital core supply voltage (DVDD to DVSS)	1.525	1.8	1.95	V
	Digital I/O supply voltage (IOVDD to DVSS)	1.1	1.8	3.6	V
ANALOG INPUTS
V_I	Analog full-scale, 0-dB input voltage (DRVDD = 3.3 V)		0.707		V_RMS
DIGITAL INPUTS
V_DIG	Digital input voltage	DVSS		IOVDD	V
TEMPERATURE
T_A	Operating free-air temperature	–40		105	°C
OTHERS
	Mono line output load resistance	10			kΩ
	Mono headphone output load resistance	16			Ω
	Digital output load capacitance		10		pF

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLV320AIC3109-Q1		UNIT
		RHB (VQFN)	RHM (VQFN)
		32 PINS	32 PINS
R_θJA	Junction-to-ambient thermal resistance	31.1	31.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	19.5	18.9	°C/W
R_θJB	Junction-to-board thermal resistance	10.6	11.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	10.6	11.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.9	0.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, f_S = 48 kHz, and 16-bit audio data (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
AUDIO ADC
	Input signal level	Single-ended configurations		0.707		V_RMS
SNR	Signal-to-noise ratio⁽¹⁾⁽²⁾	A-weighted, f_S = 48 kSPS, 0-dB PGA gain, inputs ac-shorted to ground	80	92		dB
DR	Dynamic range⁽¹⁾⁽²⁾	f_S = 48 kSPS; 0-dB PGA gain; 1-kHz, –60-dB, full-scale input signal		93		dB
THD	Total harmonic distortion	f_S = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB, full-scale input signal		–89	–75	dB
PSRR	Power-supply rejection ratio	217-Hz signal applied to DRVDD		55		dB
PSRR	Power-supply rejection ratio	1-kHz signal applied to DRVDD		44		dB
	Input channel separation	1-kHz, –2-dB, full-scale signal, MIC1 to MIC2		–71		dB
	Gain error	f_S = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB, full-scale input signal		0.82		dB
	ADC programmable-gain amplifier maximum gain	1-kHz input tone		59.5		dB
	ADC programmable-gain amplifier step size			0.5		dB
	Input resistance	MIC1/MIC2 inputs routed to single ADC input MIX attenuation = 0 dB		20		kΩ
	Input resistance	MIC1/MIC2 inputs routed to single ADC input MIX attenuation = 12 dB		80		kΩ
	Input resistance			80		kΩ
	Input capacitance	MIC1/LINE1 inputs		10		pF
	Input level control minimum attenuation setting			0		dB
	Input level control maximum attenuation setting			12		dB
	Input level control attenuation step size			1.5		dB
ANALOG PASSTHROUGH MODE
R_DS(on)	Input-to-output switch resistance	MIC1/LINE1 to LINEOUT		330		Ω
INPUT SIGNAL LEVEL, DIFFERENTIAL
SNR	Signal-to-noise ratio	A-weighted, f_S = 48 kSPS, 0-dB PGA gain, inputs ac-shorted to ground		92		dB
THD	Total harmonic distortion	f_S = 48 kHz; 0-dB PGA gain, 1-kHz, –2-dB, full-scale input signal		–94		dB
ADC DIGITAL DECIMATION FILTER (f_S = 48 kHz)
	Filter gain	From 0 f_S to 0.39 f_S		±0.1		dB
		At 0.4125 f_S		–0.25
		At 0.45 f_S		–3
		At 0.5 f_S		–17.5
		From 0.55 f_S to 64 f_S		–75
	Filter group delay			17/f_S		s
MICROPHONE BIAS
	Bias voltage	Programmable setting = 2 V		2		V
		Programmable setting = 2.5 V	2.3	2.455	2.7
		Programmable setting = AVDD		AVDD
	Current sourcing	Programmable setting = 2.5 V		4		mA
AUDIO DAC, DIFFERENTIAL LINE OUTPUT (R_LOAD = 10 kΩ)
	Full-scale output voltage	0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB		1.414		V_RMS
	Full-scale output voltage			4		V_PP
SNR	Signal-to-noise ratio⁽³⁾	A-weighted, f_S = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level	88	102		dB
DR	Dynamic range	A-weighted, f_S = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V		97		dB
THD	Total harmonic distortion	f_S = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V		–95	–75	dB
PSRR	Power-supply rejection ratio	217-Hz signal applied to DRVDD, AVDD		78		dB
PSRR	Power-supply rejection ratio	1-kHz signal applied to DRVDD, AVDD		80		dB
	DAC gain error	0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; f_S = 48 kHz		–0.2		dB
AUDIO DAC, SINGLE-ENDED LINE OUTPUT (R_LOAD = 10 kΩ)
	Full-scale output voltage	0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB		0.707		V_RMS
SNR	Signal-to-noise ratio	A-weighted, f_S = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level		96		dB
SNR	Signal-to-noise ratio	A-weighted, f_S = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode		97		dB
DR	Dynamic range	A-weighted, f_S = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V		91		dB
	DAC gain error	0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; f_S = 48 kHz		–0.85		dB
AUDIO DAC, SINGLE-ENDED HEADPHONE OUTPUT (R_LOAD = 16 Ω)
	Full-scale output voltage	0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB		0.707		V_RMS
SNR	Signal-to-noise ratio	A-weighted, f_S = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level		96		dB
SNR	Signal-to-noise ratio	A-weighted, f_S = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode		97		dB
DR	Dynamic range	A-weighted, f_S = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V		91		dB
THD	Total harmonic distortion	f_S = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V		–71	–65	dB
PSRR	Power-supply rejection ratio	217-Hz signal applied to DRVDD, AVDD		43		dB
PSRR	Power-supply rejection ratio	1-kHz signal applied to DRVDD, AVDD		41		dB
	DAC gain error	0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; f_S = 48 kHz		–0.85		dB
DAC DIGITAL INTERPOLATION FILTER (f_S = 48 kHz)
	Pass band		0		0.45 f_S	Hz
	Pass-band ripple			±0.06		dB
	Transition band		0.45 f_S		0.55 f_S	Hz
	Stop band		0.55 f_S		7.5 f_S	Hz
	Stop-band attenuation			65		dB
	Group delay			21 / f_S		s
MONO HEADPHONE DRIVER (AC-Coupled Output Configuration⁽³⁾)
	0-dB full-scale output voltage	0-dB gain to high-power outputs, output common-mode voltage setting = 1.35 V		0.707		V_RMS
	Programmable output common-mode voltage (applicable to line outputs also)	First option		1.35		V
		Second option		1.5
		Third option		1.65
		Fourth option		1.8
	Maximum programmable output level control gain			9		dB
	Programmable output level control gain step size			1		dB
P_O	Maximum output power	R_L = 32 Ω		15		mW
P_O	Maximum output power	R_L = 16 Ω		30		mW
SNR	Signal-to-noise ratio⁽⁴⁾	A-weighted		94		dB
MONO HEADPHONE DRIVER (AC-Coupled Output Configuration, continued)
THD	Total harmonic distortion	1-kHz output, P_O = 5 mW, R_L = 32 Ω		–77		dB
		1-kHz output, P_O = 5 mW, R_L = 32 Ω		0.014%
		1-kHz output, P_O = 10 mW, R_L = 32 Ω		–76		dB
		1-kHz output, P_O = 10 mW, R_L = 32 Ω		0.016%
		1-kHz output, P_O = 10 mW, R_L = 16 Ω		–73		dB
		1-kHz output, P_O = 10 mW, R_L = 16 Ω		0.022%
		1-kHz output, P_O = 20 mW, R_L = 16 Ω		–71		dB
		1-kHz output, P_O = 20 mW, R_L = 16 Ω		0.028%
	Channel separation	1-kHz, 0-dB input		90		dB
PSRR	Power-supply rejection ratio	217 Hz, 100 mV_PP on AVDD, DRVDD		48		dB
	Mute attenuation	1-kHz output		107		dB
DIGITAL I/O
V_IL	Input low level		–0.3	0.3 IOVDD		V
V_IH	Input high level⁽⁵⁾	IOVDD > 1.6 V	0.7 IOVDD			V
V_IH	Input high level⁽⁵⁾	IOVDD ≤ 1.6 V	1.1			V
V_OL	Output low level			0.1 IOVDD		V
V_OH	Output high level		0.8 IOVDD			V
CURRENT CONSUMPTION (DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V)
I_IN	I_DRVDD + I_AVDD	RESET held low		0.1		µA
	I_DVDD	RESET held low		0.2		µA
	I_DRVDD + I_AVDD	Mono ADC record, f_S = 8 kSPS, I²S slave, AGC off, no signal		2.15		mA
	I_DVDD			0.48
	I_DRVDD + I_AVDD	Mono ADC record, f_S = 48 kSPS, I²S slave, AGC off, no signal		4.31⁽⁶⁾
	I_DVDD			2.45⁽⁶⁾
	I_DRVDD + I_AVDD	Mono DAC playback to lineout, analog mixer bypassed, f_S = 48 kSPS, I²S slave		3.5
	I_DVDD			2.3
	I_DRVDD + I_AVDD	Mono DAC playback to lineout, f_S = 48 kSPS, I²S slave, no signal		4.9
	I_DVDD			2.3
	I_DRVDD + I_AVDD	Mono DAC playback to mono single-ended headphone, f_S = 48 kSPS, I²S slave, no signal		6.7
	I_DVDD			2.3
	I_DRVDD + I_AVDD	Mono line in to mono line out, no signal		3.11
	I_DVDD	Mono line in to mono line out, no signal		0
	I_DRVDD + I_AVDD	Extra power when PLL enabled		1.4
	I_DVDD	Extra power when PLL enabled		0.9
	I_DRVDD + I_AVDD	All blocks powered down, headset detection enabled, headset not inserted		28		µA
	I_DVDD			2		µA

(1) Ratio of output level with 1-kHz, full-scale, sine-wave input to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz, low-pass filter and an A-weighted filter, where noted. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) Unless otherwise noted, all measurements use an output common-mode voltage setting of 1.35 V, a 0-dB output level control gain, and a 16-Ω single-ended load.

(4) Ratio of output level with a 1-kHz, full-scale input to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to
20-kHz bandwidth.

(5) When IOVDD < 1.6 V, minimum V_IH is 1.1 V.

(6) Additional power is consumed when the PLL is powered.

6.6 Audio Data Serial Interface Timing Requirements⁽¹⁾⁽²⁾

		IOVDD = 1.1 V		IOVDD = 3.3 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
I²S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN MASTER MODE (See Figure 1)
t_d(WS)	ADWS, WCLK delay time		50		15	ns
t_d(DO-WS)	ADWS, WCLK to DOUT delay time		50		20	ns
t_d(DO-BCLK)	BCLK to DOUT delay time		50		15	ns
t_s(DI)	DIN setup time	10		6		ns
t_h(DI)	DIN hold time	10		6		ns
t_r	Rise time		30		10	ns
t_f	Fall time		30		10	ns
DSP TIMING IN MASTER MODE (See Figure 2)
t_d(WS)	ADWS, WCLK delay time		50		15	ns
t_d(DO-BCLK)	BCLK to DOUT delay time		50		15	ns
t_s(DI)	DIN setup time	10		6		ns
t_h(DI)	DIN hold time	10		6		ns
t_r	Rise time		30		10	ns
t_f	Fall time		30		10	ns
I²S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN SLAVE MODE (See Figure 3)
t_H(BCLK)	BCLK high period	70		35		ns
t_L(BCLK)	BCLK low period	70		35		ns
t_s(WS)	ADWS, WCLK setup time	10		6		ns
t_h(WS)	ADWS, WCLK hold time	10		6		ns
t_d(DO-WS)	ADWS, WCLK to DOUT delay time (for left-justified mode only)		50		35	ns
t_d(DO-BCLK)	BCLK to DOUT delay time		50		20	ns
t_s(DI)	DIN setup time	10		6		ns
t_h(DI)	DIN hold time	10		6		ns
t_r	Rise time		8		4	ns
t_f	Fall time		8		4	ns
DSP TIMING IN SLAVE MODE (See Figure 4)
t_H(BCLK)	BCLK high period	70		35		ns
t_L(BCLK)	BCLK low period	70		35		ns
t_s(WS)	ADWS, WCLK setup time	10		8		ns
t_h(WS)	ADWS, WCLK hold time	10		8		ns
t_d(DO-BCLK)	BCLK to DOUT delay time		50		20	ns
t_s(DI)	DIN setup time	10		6		ns
t_h(DI)	DIN hold time	10		6		ns
t_r	Rise time		8		4	ns
t_f	Fall time		8		4	ns