JAJSGP7B May   2012  – December 2018 TLV320DAC3203

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Bypass Outputs
    6. 6.6  Electrical Characteristics, Microphone Interface
    7. 6.7  Electrical Characteristics, Audio Outputs
    8. 6.8  Electrical Characteristics, LDO
    9. 6.9  Electrical Characteristics, Misc.
    10. 6.10 Electrical Characteristics, Logic Levels
    11. 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
    12. 6.12 Typical DSP Timing Characteristics
    13. 6.13 I2C Interface Timing
    14. 6.14 SPI Interface Timing (See )
    15. 6.15 Typical Characteristics
      1. 6.15.1 Typical Characteristics, FFT
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Connections
        1. 7.3.1.1 Digital Pins
          1. 7.3.1.1.1 Multifunction Pins
        2. 7.3.1.2 Analog Pins
      2. 7.3.2 Analog Audio I/O
        1. 7.3.2.1 Analog Low Power Bypass
        2. 7.3.2.2 Headphone Outputs
      3. 7.3.3 Digital Microphone Inteface
        1. 7.3.3.1 ADC Processing Blocks — Overview
          1. 7.3.3.1.1 Processing Blocks
      4. 7.3.4 DAC
        1. 7.3.4.1 DAC Processing Blocks — Overview
      5. 7.3.5 Powertune
      6. 7.3.6 Digital Audio I/O Interface
      7. 7.3.7 Clock Generation and PLL
      8. 7.3.8 Control Interfaces
        1. 7.3.8.1 I2C Control
        2. 7.3.8.2 SPI Control
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics, Audio Outputs

At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN, PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Audio DAC – Stereo Single-Ended Headphone Output
Device Setup Load = 16Ω (single-ended), 50pF
Headphone Output on AVdd Supply,
Input & Output CM = 0.9V, DOSR = 128,
MCLK = 256* fs, Channel Gain = 0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Full scale output voltage (0dB) 0.5 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input, modulator in excited state 88 100 dB
DR Dynamic range, A-weighted (1)(2) –60dB 1kHz input full-scale signal, Word Length = 20 bits, Power Tune = PTM_P4 99 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –80 –70 dB
DAC Gain Error 0dB, 1kHz input full scale signal ±0.1 dB
DAC Mute Attenuation Mute 127 dB
DAC channel separation –1dB, 1kHz signal, between left and right HP out 92 dB
DAC PSRR 100mVpp, 1kHz signal applied to AVdd 70 dB
100mVpp, 217Hz signal applied to AVdd 75 dB
Power Delivered RL=16Ω, Output Stage on AVdd = 1.8V
THDN < 1%, Input CM=0.9V,
Output CM=0.9V, Channel Gain = 2dB		 13 mW
RL= 16Ω Output Stage on LDOIN = 3.3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.65V, Channel Gain = 8dB		 47
Audio DAC – Stereo Single-Ended Headphone Output
Device Setup Load = 16Ω (single-ended), 50pF,
Headphone Output on AVdd Supply,
Input and Output CM = 0.75V; AVdd = 1.5V,
DOSR = 128, MCLK = 256 x fs,
Channel Gain = –2dB, word length = 20-bits;
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB) 0.375 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input, modulator in excited state 99 dB
DR Dynamic range, A-weighted (1)(2) -60dB 1 kHz input full-scale signal 98 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –84 dB
Audio DAC – Mono Differential Headphone Output
Device Setup Load = 32 Ω (differential), 50pF,
Headphone Output on LDOIN Supply
Input CM = 0.75V, Output CM = 1.5V,
AVdd=1.8V, LDOIN = 3.0V, DOSR = 128
MCLK = 256* fs, Channel (headphone driver) Gain = 5dB for full scale output signal,
word length = 16-bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB) 1778 mVRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input, modulator in excited state 101 dB
DR Dynamic range, A-weighted (1)(2) –60dB 1kHz input full-scale signal 98 dB
THD Total Harmonic Distortion –3dB full-scale, 1-kHz input signal –82 dB
Power Delivered RL = 32Ω, Output Stage on LDOIN = 3.3V,
THDN < 1%, Input CM = 0.9V,
Output CM = 1.65V, Channel Gain = 8dB		 125 mW
RL = 32Ω Output Stage on LDOIN = 3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.5V, Channel Gain = 8dB		 103 mW
(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values