JAJSGP7B May   2012  – December 2018 TLV320DAC3203

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Bypass Outputs
    6. 6.6  Electrical Characteristics, Microphone Interface
    7. 6.7  Electrical Characteristics, Audio Outputs
    8. 6.8  Electrical Characteristics, LDO
    9. 6.9  Electrical Characteristics, Misc.
    10. 6.10 Electrical Characteristics, Logic Levels
    11. 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
    12. 6.12 Typical DSP Timing Characteristics
    13. 6.13 I2C Interface Timing
    14. 6.14 SPI Interface Timing (See )
    15. 6.15 Typical Characteristics
      1. 6.15.1 Typical Characteristics, FFT
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Connections
        1. 7.3.1.1 Digital Pins
          1. 7.3.1.1.1 Multifunction Pins
        2. 7.3.1.2 Analog Pins
      2. 7.3.2 Analog Audio I/O
        1. 7.3.2.1 Analog Low Power Bypass
        2. 7.3.2.2 Headphone Outputs
      3. 7.3.3 Digital Microphone Inteface
        1. 7.3.3.1 ADC Processing Blocks — Overview
          1. 7.3.3.1.1 Processing Blocks
      4. 7.3.4 DAC
        1. 7.3.4.1 DAC Processing Blocks — Overview
      5. 7.3.5 Powertune
      6. 7.3.6 Digital Audio I/O Interface
      7. 7.3.7 Clock Generation and PLL
      8. 7.3.8 Control Interfaces
        1. 7.3.8.1 I2C Control
        2. 7.3.8.2 SPI Control
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

YZK Package
25 Pin DSBGA
Top View
RGE Package
24 Pin VQFN
Top View

Pin Functions

PIN NAME TYPE DESCRIPTION
QFN PIN WCSP BALL
1 A1 MCLK I Master Clock Input
2 B2 BCLK IO Audio serial data bus (primary) bit clock
3 B3 WCLK IO Audio serial data bus (primary) word clock
4 A2 DIN/MFP1 I Primary function
Audio serial data bus data input
Secondary function
Digital Microphone Input
General Purpose Input
5 A3 DOUT/MFP2 O Primary
Audio serial data bus data output
Secondary
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
6 A5 DMDIN/
MFP3/ 		I Primary (SPI_Select = 1)
SPI serial clock
Secondary: (SPI_Select = 0)
Digital microphone input
Headset detect input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC/common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
7 A4 SCL/
SS 		I Multi-function digital input.
For (SPI_SELECT=0): Clock Pin for I2C control bus.
For (SPI_SELECT = 1): SPI chip selection pin.
8 B4 SDA/ MOSI I/O Multi-function digital pin.
For (SPI_SELECT=0): Data Pin for I2C control bus.
For (SPI_SELECT = 1): SPI data input.
9 B5 DMCLK/
MFP4		 O Primary (SPI_Select = 1)
Serial data output
Secondary (SPI_Select = 0) Multifunction pin #4 (MFP4) options are only available using I2C
Digital microphone clock output
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
10 C5 HPR O Right high-power output driver
11 D5 LDOin Power LDO Input supply and Headphone Power supply 1.9V– 3.6V
12 D4 HPL O Left high power output driver
13 D3 AVdd Power Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
14 E4 AVss Ground Analog ground supply
15 E5 INL I Left Analog Bypass Input
16 E3 INR I Right Analog Bypass Input
17 E2 REF O Reference voltage output for filtering
18 D2 MICBIAS O Microphone bias voltage output
19 E1 SPI_ SELECT I Control mode select pin ( 1 = SPI, 0 = I2C )
20 C2 RESET I Reset (active low)
21 D1 DVss Ground Digital Ground and Chip-substrate
22 C1 DVdd Power Digital voltage supply 1.26V–1.95V
23 B1 IOVss Ground I/O ground supply
24 C3 IOVdd Power I/O voltage supply 1.1V – 3.6V
n/a C4 GPIO/MFP5 I/O Primary
General Purpose digital IO
Secondary
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output