JAJSOM8A October   2022  – December 2023 TLV3801-Q1 , TLV3802-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
      2. 7.4.2 LVDS Output
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Capacitive Loads
      2. 8.1.2 Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Optical Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Non-Inverting Comparator With Hysteresis
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Logic Clock Source to LVDS Transceiver
      4. 8.2.4 External Trigger Function for Oscilloscopes
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2 Detailed Design Procedure

Set VBIAS to be in the recommended common-mode voltage range of the OPA858. This is also the minimum output voltage of the op amp VOUT, MIN as the op amp will attempt to settle at the voltage applied to the non-inverting input.

The maximum output voltage of the op amp VOUT, MAX can be calculated from the desired output voltage swing VOUT, SWING and VOUT, MIN, as shown in Equation 2.

Equation 2. VOUT, MAX = VOUT, SWING + VOUT, MIN
The gain resistor RF is determined by the desired VOUT, MAX and VOUT, MIN and the maximum current IDIODE through the diode, as shown in Equation 2.

Equation 3. RF = (VOUT, MAX - VOUT, MIN) / IDIODE
The feedback capacitor, in combinaton with the gain resistor, forms a pole in the frequency response of the amplifier. The feedback capacitor can be determined by the gain resistor and the desired pole frequency fp, as shown in Equation 2.

Equation 4. CF = 1 / (2 × π × RF x fp)

Set VREF to be the switching threshold voltage between VOUT, MAX and VOUT, MIN.

Select values for VBIAS and VREF. Plug in given values for VOUT, MAX, IDIODE, and fp. For the given example, VBIAS = 1.5 V, VREF = 1.55 V, and RF, CF is solved as 1 kΩ and 1 pF, respectively.

For more information, please refer to the op amp tutorials for stability analysis on the transimpedance amplifier Spice Stability Analysis and Op Amp Stability. See application note SBOA268A Transimpedance Amplifier Circuit for more detailed procedures.