SBVS404A April   2020  – June 2020 TLV4062 , TLV4082

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram for TLV4062
      2.      Block Diagram for TLV4082
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs (IN1, IN2)
      2. 7.4.2 Outputs (OUT1, OUT2)
      3. 7.4.3 Switching Threshold and Hysteresis
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Threshold Overdrive
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Two Separate Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Early Warning Detection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Additional Application Information
        1. 8.2.3.1 Pull-Up Resistor Selection
        2. 8.2.3.2 INx Capacitor
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Related Links
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Detailed Design Procedure

Configure the circuit as shown in Figure 25. Connect V+ to a 3.3 V power rail and connect V- to ground. The resistor network is used to create an early warning detection signal at OUT2, which will give a warning alert as VMON approaches the max limit, changing state from a logic low to a logic high. OUT2 will stay high for a longer period until VMON is no longer in the warning zone. OUT1 will be used when VMON reaches the max limit and transition from a logic low to a logic high. This type of topology can be used for sensitive systems where advanced notice of the power supply over-voltage detection is needed.

Use VMON2, the threshold for a low to high transition at OUT2, IIN_RES, the current flow through the resistor network, to determine the minimum total resistance necessary to achieve the current consumption specification.

Equation 5. TLV4062 TLV4082 eq1_2.gif

where

  • VMON2 is the target voltage at which OUT2 goes high when VMON rises
  • IIN_RES is the current flowing through the resistor network

After RTOTAL is determined, R3 can be calculated using Equation 6. Select the nearest 1% resistor value for R3. In this case, 845 kΩ is the closest value.

Equation 6. TLV4062 TLV4082 eq2_2.gif

Use the voltage divider equation Equation 7 The voltage divider equation controls the V MON1 voltage at which OUT1 will transition from a logic high to a logic low.

Equation 7. TLV4062 TLV4082 eq3_2.gif

where

  • VMON1 is the target voltage at which OUT1 goes low when VMON falls

Rearranging Equation 7 to solve for R2 yields Equation 8Select the nearest 1% resistor value for R2. In this case, 55.6kΩ is the closest value.

Equation 8. TLV4062 TLV4082 eq4_2.gif

Use Equation 9 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 1.87 MΩ is a 1% resistor.

Equation 9. TLV4062 TLV4082 eq5_2.gif