JAJSPA9 October   2020 TLV4062-Q1 , TLV4082-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs (IN1, IN2)
      2. 7.4.2 Outputs (OUT1, OUT2)
      3. 7.4.3 Switching Threshold and Hysteresis
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Threshold Overdrive
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Two Separate Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Early Warning Detection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Additional Application Information
        1. 8.2.3.1 Pull-Up Resistor Selection
        2. 8.2.3.2 INx Capacitor
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-4DF305CA-B27C-4F5A-B3C4-5023845D4BFA-low.gifFigure 5-1 DBV Package, 6-Pin SOT-23
Table 5-1 Pin Functions
NAME NO. I/O DESCRIPTION
DBV
GND 5 — Ground
OUT1 2 O OUT1 is the output for IN1. OUT1 is asserted (driven low) when the voltage at IN1 falls below VIT–. OUT1 is deasserted (goes high) after IN1 rises higher than VIT+.
OUT1 is a push-pull output for the TLV4062 and an open-drain output for the TLV4082.
The open-drain device (TLV4082) can be pulled up to 5.5 V independent of V+; a pullup resistor is required for this device.
OUT2 3 O OUT2 is the output for IN2. OUT2 is asserted (driven low) when the voltage at IN2 falls below VIT–. OUT2 is deasserted (goes high) after IN2 rises higher than VIT+.
OUT2 is a push-pull output for the TLV4062 and an open-drain output for the TLV4082.
The open-drain device (TLV4082) can be pulled up to 5.5 V independent of V+; a pullup resistor is required for this device.
IN1 6 I This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT–), OUT1 is asserted.
IN2 4 I This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT–), OUT2 is asserted.
V+ 1 I Supply voltage input. Connect a 1.5-V to 5.5-V supply to V+ in order to power the device. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin (required for V+ < 1.5 V).