SBVS404A April   2020  – June 2020 TLV4062 , TLV4082

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram for TLV4062
      2.      Block Diagram for TLV4082
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs (IN1, IN2)
      2. 7.4.2 Outputs (OUT1, OUT2)
      3. 7.4.3 Switching Threshold and Hysteresis
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Threshold Overdrive
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Two Separate Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Early Warning Detection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Additional Application Information
        1. 8.2.3.1 Pull-Up Resistor Selection
        2. 8.2.3.2 INx Capacitor
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Related Links
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3.1 Pull-Up Resistor Selection

For the TLV4082 (open-drain outputs), care should be taken in selecting the pull-up resistor (RPU) value to ensure proper output voltage levels. First, consider the required output high logic level requirement of the logic device that is being drive by the comparator when calculating the maximum RPU value. When in a logic high output state, the output impedance of the comparator is very high but there is finite amount of leakage current that needs to be accounted for. Use the | Ilkg(OD)| from the EC table and the VIH (min) of the logic device being driven by the TLV4082 to determine RPU using Equation 10 .

Equation 10. TLV4062 TLV4082 RPU_max.gif

Next determine the minimum value for RPU by using the VIL (max) of the logic device being driven by the TLV4082. In order for the comparator output to be recognized as a logic low, VIL (max) is used to determine the upper boundary of the comparator's VOL. VOL (max) for the comparator is available in the EC table from specific sink current levels and can be found from the VOUT versus ISINK curve in the Typical Applications curve. A good design practice is to choose a value for VOL that is ½ the value of VIL for the input logic device. The corresponding sink current and VOL value will be needed to calculate the minimum RPU. This method will ensure enough noise margin for the logic low level. With iSINK determined and the corresponding RPU obtained, the minimum ) is calculated with Equation 11.

Equation 11. TLV4062 TLV4082 RPU_min.gif

Since the range of possible RPU values is large, a value between 5 kΩ and 100kΩ is generally recommended. A smaller RPU value provides faster output transition time and better noise immunity, while a larger RPU value consumes less power when in a logic low output state.