JAJSEY2Y July   1996  – March 2024 TLV431 , TLV431A , TLV431B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics for TLV431
    6. 5.6 Electrical Characteristics for TLV431A
    7. 5.7 Electrical Characteristics for TLV431B
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Open Loop (Comparator)
      2. 7.4.2 Closed Loop
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Comparator with Integrated Reference (Open Loop)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Basic Operation
          2. 8.2.1.2.2 Overdrive
          3. 8.2.1.2.3 Output Voltage and Logic Input Level
            1. 8.2.1.2.3.1 Input Resistance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Shunt Regulator/Reference
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Programming Output/Cathode Voltage
          2. 8.2.2.2.2 Total Accuracy
          3. 8.2.2.2.3 Stability
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DBZ|3
  • DBV|5
  • PK|3
  • LP|3
サーマルパッド・メカニカル・データ
発注情報

5.7 Electrical Characteristics for TLV431B

at 25°C free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TLV431B UNIT
MIN TYP MAX
VREF Reference voltage VKA = VREF, IK=10mA TA = 25°C 1.234 1.24 1.246 V
TA = full range (1) (see Figure 6-1) TLV431BC 1.227 1.253
TLV431BI 1.224 1.259
TLV431BQ 1.221 1.265
VREF(dev) VREF deviation over full temperature range (2) VKA = VREF , IK = 10mA (1) (see Figure 6-1) TLV431BC 4 12 mV
TLV431BI 6 20
TLV431BQ 11 31
GUID-D3FB9B8F-07E7-48BF-BEA6-62A425202AE8-low.png
Ratio of VREF change in cathode voltage change VKA = VREF to 6V, IK = 10mA (see Figure 6-2) -1.5 -2.7 mV/V
Iref Reference terminal current IK = 10mA, R1 = 10kΩ, R2 = open (see Figure 6-2) 0.1 0.5 µA
Iref(dev) Iref deviation over full temperature range (2) IK = 10mA, R1 =10kΩ, R2 = open (3) (see Figure 6-2) TLV431BC 0.05 0.3 µA
TLV431BI 0.1 0.4
TLV431BQ 0.15 0.5
IK(min) Minimum cathode current for regulation VKA = VREF (see Figure 6-1) 55 100 µA
IK(off) Off-state cathode current VREF = 0, VKA = 6V (see Figure 6-3) 0.001 0.1 µA
|zKA| Dynamic impedance (4) VKA = VREF, f ≤ 1kHz, IK = 0.1mA to 15mA (see Figure 6-1) 0.25 0.4 Ω
(1) Full temperature ranges are –40°C to 125°C for TLV431Q, –40°C to 85°C for TLV431I, and 0°C to 70°C for TLV431C.
(2) The deviation parameters VREF(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over the rated temperature range. The average full-range temperature coefficient of the reference input voltage, αVREF, is defined as:
GUID-51ACCAD2-A6D0-4180-AAAE-DC4F5EDF5296-low.png
where ΔTA is the rated operating free-air temperature range of the device. αVREF can be positive or negative, depending on whether minimum VREF or maximum VREF, respectively, occurs at the lower temperature.
(3) Full temperature ranges are –40°C to 125°C for TLV431Q, –40°C to 85°C for TLV431I, and 0°C to 70°C for TLV431C.
(4) dynamic impedance is defined as GUID-120ADA56-9127-4C9C-BD4D-CDD20CC40987-low.png. When the device is operating with two external resistors (see Figure 6-2), the total dynamic impedance of the circuit is defined as: GUID-7EDE8785-7B7D-42B2-81ED-C15DF1D11E8E-low.png