JAJSEY2Y July   1996  – March 2024 TLV431 , TLV431A , TLV431B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics for TLV431
    6. 5.6 Electrical Characteristics for TLV431A
    7. 5.7 Electrical Characteristics for TLV431B
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Open Loop (Comparator)
      2. 7.4.2 Closed Loop
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Comparator with Integrated Reference (Open Loop)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Basic Operation
          2. 8.2.1.2.2 Overdrive
          3. 8.2.1.2.3 Output Voltage and Logic Input Level
            1. 8.2.1.2.3.1 Input Resistance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Shunt Regulator/Reference
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Programming Output/Cathode Voltage
          2. 8.2.2.2.2 Total Accuracy
          3. 8.2.2.2.3 Stability
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBZ|3
  • DBV|5
  • PK|3
  • DCK|6
  • LP|3
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-928C1AF5-4FE1-4789-B561-37D5EC1DCF31-low.pngFigure 4-1 D (SOIC) Package
(Top View)
GUID-ABA9AFF1-DA44-432F-A249-88DB28BEA643-low.pngFigure 4-3 DBZ (SOT-23-3) Package
(Top View)
GUID-BA657DD6-2FDB-453D-9DE0-02CA4D2486A6-low.pngFigure 4-5 DCK (SC-70) Package
(Top View)
GUID-7AA54F89-6A1A-4696-A3EA-5386496E26A8-low.png

NC − No internal connection

* Pin 2 is attached to Substrate and must be connected to ANODE or left open.

Figure 4-2 DBV (SOT-23-5) Package
(Top View)
GUID-C9C4227B-53AE-4495-AF68-1D1406CEA76E-low.pngFigure 4-4 PK (SOT-89) Package
(Top View)
GUID-40B907EA-22A2-4268-AC7A-0B2E493360E2-low.pngFigure 4-6 LP (TO-92/TO-226) Package
(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME DBZ DBV PK D LP DCK
CATHODE 2 3 3 1 1 1 I/O Shunt Current/Voltage input
REF 1 4 1 8 3 3 I Threshold relative to common anode
ANODE 3 5 2 2, 3, 6, 7 2 6 O Common pin, normally connected to ground
NC — 1 — 4, 5 — 2, 4, 5 I No Internal Connection
* — 2 — — — — I Substrate Connection