JAJSBR6E February   2012  – September 2016 TLV62150 , TLV62150A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable / Shutdown (EN)
      2. 8.3.2 Soft Start / Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Pin-Selectable Output Voltage (DEF)
      5. 8.3.5 Frequency Selection (FSW)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 External Component Selection
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Capacitor Selection
            1. 9.2.2.2.2.1 Output Capacitor
            2. 9.2.2.2.2.2 Input Capacitor
            3. 9.2.2.2.2.3 Soft-Start Capacitor
        3. 9.2.2.3 Tracking Function
        4. 9.2.2.4 Output Filter and Loop Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 LED Power Supply
      2. 9.3.2 Active Output Discharge
      3. 9.3.3 Inverting Power Supply
      4. 9.3.4 Various Output Voltages
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 関連リンク
    3. 12.3 ドキュメントのサポート
      1. 12.3.1 関連資料
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGT|16
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Pin voltage (2) AVIN, PVIN –0.3 20 V
EN, SS/TR –0.3 VIN+0.3
SW –0.3 VIN+0.3 V
DEF, FSW, FB, PG, VOS –0.3 7 V
Power Good sink current PG 10 mA
Operating junction temperature TJ –40 125 °C
Storage temperature Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge(1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) ±500
(1) ESD testing is performed according to the respective JESD22 JEDEC standard.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIX MAX UNIT
Supply Voltage 4 17 V
Temperature Range, TA –40 85 °C
Operating junction temperature, TJ –40 125

7.4 Thermal Information

THERMAL METRIC(1) TLV62150 UNIT
RGT [VQFN]
16 PINS
RθJA Junction-to-ambient thermal resistance 45 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.6 °C/W
RθJB Junction-to-board thermal resistance 17.4 °C/W
ψJT Junction-to-top characterization parameter 1.1 °C/W
ψJB Junction-to-board characterization parameter 17.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (TA = –40°C to 85°C), typical values at VIN = 12 V and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input Voltage Range(1) 4 17 V
IQ Operating Quiescent Current EN=High, IOUT=0 mA, device not switching 19 27 μA
ISD Shutdown Current (2) EN=Low 1.5 4 μA
VUVLO Undervoltage Lockout Threshold Falling Input Voltage (PWM mode operation) 2.6 2.7 2.8 V
Hysteresis 200 mV
TSD Thermal Shutdown Temperature 160 °C
Thermal Shutdown Hysteresis 20
CONTROL (EN, DEF, FSW, SS/TR, PG)
VH High Level Input Threshold Voltage (EN, DEF, FSW) 0.9 V
VL Low Level Input Threshold Voltage (EN, DEF, FSW) 0.3 V
ILKG Input Leakage Current (EN, DEF, FSW) EN=VIN or GND; DEF, FSW=VOUT or GND 0.01 1 μA
VTH_PG Power Good Threshold Voltage Rising (%VOUT) 92% 95% 98%
Falling (%VOUT) 87% 90% 94%
VOL_PG Power Good Output Low IPG=-2 mA 0.07 0.3 V
ILKG_PG Input Leakage Current (PG) VPG=1.8 V 1 400 nA
ISS/TR SS/TR Pin Source Current 2.3 2.5 2.7 μA
POWER SWITCH
RDS(ON) High-Side MOSFET ON-Resistance VIN≥6 V 90 mΩ
Low-Side MOSFET ON-Resistance VIN≥6 V 40 mΩ
ILIMF High-Side MOSFET Forward Current Limit(3) VIN =12 V, TA=25°C 1.4 1.7 A
OUTPUT
ILKG_FB Input Leakage Current (FB) VFB=0.8 V 1 100 nA
VOUT Output Voltage Range VIN ≥ VOUT 0.9 5 V
DEF (Output Voltage Programming) DEF=0 (GND) VOUT
DEF=1 (VOUT) VOUT+5%
Initial Output Voltage Accuracy(4) PWM mode operation, VIN ≥ VOUT +1 V 780 800 820 mV
Load Regulation(5) VIN=12 V, VOUT=3.3 V, PWM mode operation 0.05 %/A
Line Regulation(5) 4 V ≤ VIN ≤ 17 V, VOUT=3.3 V, IOUT= 1 A, PWM mode operation 0.02 %/V
(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into AVIN+PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection).
(4) This is the accuracy provided by the device itself (line and load regulation effects are not included).
(5) Line and load regulation depend on external component selection and layout (see Figure 20 and Figure 21).

7.6 Typical Characteristics

TLV62150 TLV62150A SLVSB71_IQ.png
Figure 1. Quiescent Current
TLV62150 TLV62150A SLVSAL5_RDSonHS.gif
Figure 3. High-Side Switch Resistance
TLV62150 TLV62150A SLVSB71_ISD.png
Figure 2. Shutdown Current
TLV62150 TLV62150A SLVSAL5_RDSonLS.gif
Figure 4. Low-Side Switch Resistance