JAJSED6D August   2013  – July 2019 TLV702-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Undervoltage Lockout
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermal Consideration
      2. 10.1.2 Package Mounting
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 SPICEモデル
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Typical Characteristics

Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
TLV702-Q1 tc_line_reg_10ma_lvsag6.gif
Figure 1. Line Regulation
TLV702-Q1 tc_load_reg_lvsag6.gif
Figure 3. Load Regulation
TLV702-Q1 tc_vdo_iout_lvsag6.gif
Figure 5. Dropout Voltage vs Output Current
TLV702-Q1 tc_ignd_vin_lvsag6.gif
Figure 7. Ground Pin Current vs Input Voltage
TLV702-Q1 tc_ignd-tmp_lvsag6.gif
Figure 9. Ground Pin Current vs Temperature
TLV702-Q1 tc_ilim-vin_lvsag6.gif
Figure 11. Current Limit vs Input Voltage
TLV702-Q1 tc_psrr-vin_lvsag6.gif
Figure 13. Power-Supply Ripple Rejection vs Input Voltage
TLV702-Q1 tc_load_tran_200_lvsag6.gif
Figure 15. Load Transient Response
TLV702-Q1 tc_load_tran_50_lvsag6.gif
Figure 17. Load Transient Response
TLV702-Q1 tc_line_tran_300ma_lvsag6.gif
Figure 19. Line Transient Response
TLV702-Q1 tc_line_tran_55v_lvsag6.gif
Figure 21. Line Transient Response
TLV702-Q1 tc_line_reg_300ma_lvsag6.gif
Figure 2. Line Regulation
TLV702-Q1 tc_vdo_vin_lvsag6.gif
Figure 4. Dropout Voltage vs Input Voltage
TLV702-Q1 tc_vout-tmp_lvsag6.gif
Figure 6. Output Voltage vs Temperature
TLV702-Q1 tc_ignd_iout_lvsag6.gif
Figure 8. Ground Pin Current vs Load
TLV702-Q1 tc_ishdn-vin_lvsag6.gif
Figure 10. Shutdown Current vs Input Voltage
TLV702-Q1 tc_psrr_fqcy_05v_lvsa00.gif
Figure 12. Power-Supply Ripple Rejection vs Frequency
TLV702-Q1 tc_noise-frq_lvsag6.gif
Figure 14. Output Spectral Noise Density vs Frequency
TLV702-Q1 tc_load_tran_10_lvsag6.gif
Figure 16. Load Transient Response
TLV702-Q1 tc_load_tran_300_lvsag6.gif
Figure 18. Load Transient Response
TLV702-Q1 tc_line_tran_1ma_lvsag6.gif
Figure 20. Line Transient Response
TLV702-Q1 tc_ramp_up_down_lvsag6.gif
Figure 22. VIN Ramp Up, Ramp Down Response