JAJSJ01D May   2020  – February 2023 TLV7031-Q1 , TLV7032-Q1 , TLV7034-Q1 , TLV7041-Q1 , TLV7042-Q1 , TLV7044-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions: TLV7032/42
    2. 5.1 Pin Functions: TLV7034/44
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information (Single)
    5. 6.5  Thermal Information (Dual)
    6. 6.6  Thermal Information (Quad)
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics
    9. 6.9  Electrical Characteristics (Dual)
    10. 6.10 Switching Characteristics (Dual)
    11. 6.11 Electrical Characteristics (Quad)
    12. 6.12 Switching Characteristics (Quad)
    13. 6.13 Timing Diagrams
    14. 6.14 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
      2. 7.4.2 Internal Hysteresis
      3. 7.4.3 Output
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Inverting Comparator With Hysteresis for TLV703x-Q1
      2. 8.1.2 Noninverting Comparator With Hysteresis for TLV703x-Q1
    2. 8.2 Typical Applications
      1. 8.2.1 Window Comparator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 IR Receiver Analog Front End
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Square-Wave Oscillator
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Figure 10-1 shows the typical connections for the TLV7031-Q1. To minimize supply noise, power supplies must be capacitively decoupled by a 0.1-µF ceramic capacitor in parallel with a 10-µF electrolytic capacitor. Comparators are very sensitive to input noise. Proper grounding (the use of a ground plane) helps to maintain the specified performance of the TLV70x1-Q1 family.

For best results, maintain the following layout guidelines:

  1. Use a printed-circuit board (PCB) with a good, unbroken low-inductance ground plane.
  2. Place a decoupling capacitor (0.1-µF ceramic, surface-mount capacitor) as close as possible to VCC.
  3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback around the comparator. Keep inputs away from the output.
  4. Solder the device directly to the PCB rather than using a socket.
  5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less) placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some degradation to propagation delay when the impedance is low. The top-side ground plane runs between the output and inputs.
  6. The ground pin ground trace runs under the device up to the bypass capacitor, shielding the inputs from the outputs.