JAJSHO5C October 2014 – July 2019 TLV733P
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
DQN | DBV | |||
EN | 3 | 3 | I | Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.
Drive EN less than VEN(LO) to put the LDO into shutdown mode. |
GND | 2 | 2 | — | Ground pin |
IN | 4 | 1 | I | Input pin. A small capacitor is recommended from this pin to ground.
See the Input and Output Capacitor Selection section for more details. |
NC | N/A | 4 | — | No internal connection |
OUT | 1 | 5 | O | Regulated output voltage pin. For best transient response, use a small 1-μF ceramic capacitor from this pin to ground.
See the Input and Output Capacitor Selectionsection for more details. |
Thermal pad | — | — | The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance. |