JAJSHL1J August   2018  – May 2021 TLV803E , TLV809E , TLV810E

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
      2. 8.3.2 VDD Hysteresis
      3. 8.3.3 VDD Glitch Immunity
      4. 8.3.4 Manual Reset (MR) Input for X2SON (DPW) Package Only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Voltage Rail Monitoring
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application - Overvoltage Monitoring
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 VDD Glitch Immunity

These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on both pulse duration (tGI) found in Section 7.6 and transient overdrive. Overdrive is defined by how much VDD exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1.

Equation 1. Overdrive = | (VDD / (VIT– – 1)) × 100% |

where

  • VIT– is the threshold voltage
  • VDD is the input voltage crossing VIT–
GUID-765EA975-312B-4CBC-A4A2-44F774CE2600-low.gifFigure 8-1 Overdrive Versus Pulse Duration

TLV803E, TLV809E, and TLV810E devices have built-in glitch immunity (tGI) of 10 µs typical as shown in
Section 7.6. Figure 8-2 shows that VDD must fall below VIT- for tGI, otherwise the faling transistion is ignored. When VDD falls below VIT- for tGI, RESET transitions low to indicate a fault condition after the propagation delay high-to-low (tPDHL). When VDD rises above VIT+, RESET only deasserts to logic high indicating there is no more fault condition only if VDD remains above VIT+ for longer than the reset delay (tD).

GUID-5F5CFA91-BC4D-4E82-9F61-CC55538E610A-low.gifFigure 8-2 Glitch Immunity when VDD Rises Above VIT+ for Less than RESET Delay (TLV803EA29)