SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20201027-CA0I-S25M-S0JK-CPWNF6HCFGDT-low.svgFigure 6-1 Pin Configuration TLV840M-Q1
DBV Package 5-Pin SOT-23
TLV840M-Q1 Top View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
PIN NO. TLV840MAxL-Q1 TLV840MAxH-Q1
1 RESET N/A O Active-Low Output Reset Signal: This pin is driven logic low when VDD voltage falls below the negative voltage threshold (VIT-). RESET remains low (asserted) for the delay time period (tD) after VDD voltage rises above VIT+ = VIT-+VHYS.
1 N/A RESET O Active-High Output Reset Signal: This pin is driven logic high when VDD voltage falls below the negative voltage threshold (VIT-). RESET remains high (asserted) for the delay time period (tD) after VDD voltage rises above VIT+ = VIT-+VHYS.
2 VDD VDD I Input Supply Voltage: TLV840-Q1 monitors VDD voltage
3 GND GND _ Ground
4 MR MR I Manual Reset: Pull this pin to a logic low to assert a reset signal in the RESET output pin. After MR pin is left floating or pulls to logic high, the RESET output deasserts to the nominal state after the reset delay time (tD) expires.
5 CT CT - Capacitor Time Delay Pin: The CT pin offers a user-programmable delay time. Connect an external capacitor on this pin to adjust time delay. When not in use leave pin floating for the smallest fixed time delay.