SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

Qualified for automotive applications:

  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C7B

Designed for high performance:

  • Nano supply current : 120 nA (Typ)
  • High accuracy: ±0.5% (Typ)
  • Built-in hysteresis (VHYS): 5% (Typ)
  • Fixed threshold voltage (VIT-): 0.8 V to 5.4 V

Designed for a wide range of applications:

  • Operating voltage range : 0.7 V to 6 V
  • Fixed (VIT-) voltage: 0.8 V to 5.4 V in 0.1 V steps
  • Programmable reset time delay (tD)
    • Min time delay: 40 µs (typ) without capacitor
  • Active-low manual reset (MR)

Multiple output topologies / Package type:

  • Four output topologies (RESET / RESET):
    • TLV840MADL-Q1: open-drain, active-low
    • TLV840MAPL-Q1: push-pull, active-low
    • TLV840MADH-Q1: open-drain, active-high
    • TLV840MAPH-Q1: push-pull, active-high
  • Package: SOT23-5 (DBV)